74LS73NA+2 datasheet, PDF - EEWORLD Datasheet

74LS73NA+2: DescriptionJ-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PDIP14,; Categorylogic logic; File Size206KB，4 Pages; ManufacturerRaytheon Company; Websitehttps://www.raytheon.com/

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74LS73NA+2 Overview

J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PDIP14,

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	DIP, DIP14,.3
Reach Compliance Code	unknown
Is Samacsys	N
JESD-30 code	R-PDIP-T14
JESD-609 code	e0
Logic integrated circuit type	J-K FLIP-FLOP
Number of functions	2
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Trigger type	NEGATIVE EDGE
Base Number Matches	1

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