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Audio Switching Amplifier
AD1990
FEATURES
Integrated stereo modulator and power stage
<0.002% THD + N
101 dB dynamic range (A-weighted)
2 × 5 W output power (4 Ω, <0.01% THD + N)
R
DS-ON
< 0.3 Ω (per transistor)
PSRR > 65 dB
On-off-mute pop noise suppression
EMI optimized modulator
Short-circuit protection
Overtemperature protection
Low cost DMOS process
GENERAL DESCRIPTION
The AD1990 is a 2-channel, bridge tied load (BTL), switching
audio power amplifier with integrated Σ-Δ modulator. The
modulator accepts a single-ended, analog input signal and
converts it to a switching waveform to drive speakers directly. A
digital, microprocessor-compatible interface provides control of
reset, mute, and PGA gain, as well as feedback signals for thermal
and overcurrent error conditions. The output stage can operate
over a power supply voltages range of 8 V to 12 V. The analog
modulator and digital logic operate from a 5 V supply.
APPLICATIONS
Advanced televisions
Compact multimedia systems
Minicomponents
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK
NETWORK
PGA1
PGA0
AV
DD
NFL+
NFL–
DV
DD
PV
DD
AD1990
AINL
PGA
Σ-Δ
MODULATOR
A1
A2
OUTL+
B1
LEVEL
SHIFTER
AND
DEAD TIME
CONTROL
AINR
PGA
Σ-Δ
MODULATOR
B2
H-BRIDGE
C1
C2
CLKI
CLKO
OSCILLATOR
MODE CONTROL
LOGIC AND
POP/CLICK
SUPPRESSION
D1
REF_FILT
VOLTAGE
REFERENCE
D2
OUTR–
OUTL–
OUTR+
MUTE
RESET
NFR–
DCTRL2
DCTRL1
DCTRL0
ERR2
ERR1
ERR0
NFR+
AGND
PGND
FEEDBACK
NETWORK
05380-001
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD1990
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 11
Overview ..................................................................................... 11
Σ-Δ Modulator............................................................................ 11
MUTE and RESET ..................................................................... 11
Gain Structure............................................................................. 11
Power Stage ................................................................................. 13
Clocking....................................................................................... 13
Protection Circuits and Error Reporting ................................ 14
Application Circuits ....................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
4/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD1990
SPECIFICATIONS
Test conditions, unless otherwise specified.
Table 1.
Parameter
SUPPLY VOLTAGES
AV
DD
DV
DD
PV
DD
AMBIENT TEMPERATURE
LOAD IMPEDANCE
CLOCK FREQUENCY
PGA GAIN
MEASUREMENT BANDWIDTH
Ratings
5V
5V
12 V
25°C
6Ω
12.288 MHz
0 dB
20 Hz to 20 kHz
Table 2.
Parameter
R
DS-ON
Per High-Side Transistor
Per Low-Side Transistor
MAXIMUM CURRENT THROUGH OUTx
THERMAL WARNING ACTIVE
THERMAL SHUTDOWN ACTIVE
RESTORE TEMPERATURE AFTER THERMAL SHUTDOWN
Min
Typ
260
210
5
135
150
120
Max
355
265
Unit
mΩ
mΩ
A
°C
°C
°C
Test Conditions/Comments
T = 25°C
T = 25°C
Peak
Die temperature
Die temperature
Die temperature
Table 3. Performance Specifications
Parameter
TOTAL HARMONIC DISTORTION AND NOISE (THD + N)
Typ
0.003
0.006
0.01
0.02
102
102
−100
Unit
%
%
%
%
dB
dB
dB
Test Conditions/Comments
PGA = 0 dB, P
O
= 1 W, 1 kHz
PGA = 6 dB, P
O
= 1 W, 1 kHz
PGA = 12 dB, P
O
= 1 W, 1 kHz
PGA = 18 dB, P
O
= 1 W, 1 kHz
1 kHz, A-weighted, 0 dB referred to 1% THD + N output
1 kHz, A-weighted, −60 dB referred to 1% THD + N output
PGA = 0 dB, P
O
= 5 W, 1 kHz
SIGNAL-TO-NOISE RATIO (SNR)
DYNAMIC RANGE (DNR)
CROSSTALK (LEFT-TO-RIGHT OR RIGHT-TO-LEFT)
Table 4. DC Specifications
Parameter
INPUT IMPEDANCE
OUTPUT DC OFFSET
Typ
20
±4
Unit
kΩ
mV
Test Conditions/Comments
AINL, AINR input pins
Independent of PGA setting
Rev. 0 | Page 3 of 16
AD1990
Table 5. Power Supplies
Parameter
ANALOG SUPPLY, AV
DD
DIGITAL SUPPLY, DV
DD
POWER TRANSISTOR SUPPLY, PV
DD
RESET/POWER-DOWN CURRENT
AV
DD
DV
DD
PV
DD
QUIESCENT CURRENT
AV
DD
DV
DD
PV
DD
OPERATING CURRENT
AV
DD
DV
DD
PV
DD
Min
4.5
4.5
6.5
Typ
5.0
5.0
8 to 12
0.6
7.5
19
20
5.5
30
20
5.5
218
27
7
260
Max
5.5
5.5
15
1
11
40
Unit
V
V
V
μA
μA
μA
mA
mA
mA
mA
mA
mA
Test Conditions/Comments
RESET held low
5V
5V
12 V
Inputs grounded, nonoverlap = minimum
5V
5V
12 V
V
IN
= 1 V rms, R
L
= 6 Ω, P
O
= 1 W
5V
5V
12 V
Table 6. Digital I/O
Parameter
INPUT LOGIC HIGH
INPUT LOGIC LOW
OUTPUT LOGIC HIGH
OUTPUT LOGIC LOW
LEAKAGE CURRENT ON DIGITAL OUTPUTS
Min
2.0
2.4
0.4
10
Typ
Max
0.8
Unit
V
V
V
V
μA
Test Conditions/Comments
@ 4 mA
@ 4 mA
Table 7. Digital Timing
Parameter
t
MD
t
UD
Typ
10
34
Unit
μs
μs
Test Conditions/Comments
Delay after MUTE is asserted until output stops switching
Delay after MUTE is deasserted until output starts switching
t
MD
MUTE
t
UD
OUTx
Figure 2. Mute and Unmute Delay Timing
Rev. 0 | Page 4 of 16
05380-002
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