TRANSISTOR OUTLINE PACKAGES
Q-TECH
Description
CORPORATION
TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS
1.8 to 15Vdc - 0.045Hz to 125MHz
Q-Tech’s Transistor Outline package crystal oscillators
consist of a source clock square wave generator, logic
output buffers and/or logic divider stages, and a round AT
high-precision quartz crystal built in an all metal TO
package.
Features
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Made in the USA
ECCN: EAR99
DFARS (Berry Amendment) Compliant
USML Registration # M17677
Wide frequency range from 0.045Hz to 125MHz
Available as QPL MIL-PRF-55310/09 and/10 (TTL)
and /12 (CMOS)
Choice of TO packages and pin outs
Choice of supply voltages
Choice of output logic options ( CMOS, ACMOS,
HCMOS, LVHCMOS, and TTL)
AT-Cut crystal
All metal hermetically sealed package
Tight or custom symmetry available
Low height available
External tuning capacitor option
Fundamental and third overtone designs
Tristate function option D
Three-point crystal mounts
Custom design available tailors to meet customer’s
needs
Q-Tech does not use pure lead or pure tin in its
products
RoHS compliant
Ordering Information
Model #
C
AC
HC
T
L
N
R
Z
=
=
=
=
=
=
=
=
QTXX — XX — D — XX — M — 60.000MHz
Tristate Option D
(Left blank if no Tristate)
CMOS +5V to +15V *
ACMOS +5V
HCMOS +5V
TTL +5V
LVHCMOS + 3.3V
LVHCMOS + 2.5V
LVHCMOS + 1.8V
Z output
Screened to
MIL-PRF-55310,level B
(Left blank if no screening)
Output frequency
For frequency stability vs. temperature options not listed herein, please request a
custom part number.
1
= ± 100ppm at
0ºC to +70ºC
3** = ± 5ppm at
0ºC to +50ºC
4
= ± 50ppm at
0ºC to +70ºC
5
= ± 25ppm at -20ºC to +70ºC
6
= ± 50ppm at -55ºC to +105ºC
9
= ± 50ppm at -55ºC to +125ºC
10
= ± 100ppm at -55ºC to +125ºC
11
= ± 50ppm at -40ºC to +85ºC
12
= ± 100ppm at -40ºC to +85ºC
(*) Please specify supply voltage when ordering CMOS
(**) Require an external capacitor
Applications
• Designed to meet today’s requirements for all voltage
applications
• Wide military clock applications
• Industrial controls
• Microcontroller driver
Packaging Options
For Non-Standard requirements, contact Q-Tech Corporation at
Sales@Q-Tech.com
• Standard packaging in black foam
• Solder Dip Sn/Pb 60/40%
• P. I. N. D. test
• Lead trimming
Other Options Available For An Additional Charge
All Transistor Outline packages are available in surface mount form.
Specifications subject to change without prior notice.
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-t ec h.com
Transistor Outline Packages (Revision A, May 2008) (ECO# 9304)
1
TRANSISTOR OUTLINE PACKAGES
Electrical Characteristics
Parameters
Output freq. range (Fo)
Supply voltage (Vdd)
Freq. stability (∆F/∆T)
Storage temp. (Tsto)
QT2
QT3
QT1, 14
CORPORATION
Q-TECH
TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS
1.8 to 15Vdc - 0.045Hz to 125MHz
C
244Hz — 15MHz
5V ~ 15Vdc ± 10%
AC
732.4Hz — 85MHz
5.0Vdc ± 10%
0.045Hz — 85MHz
732.4Hz — 85MHz
HC
T
732.4Hz — 125MHz
0.045Hz — 85MHz
3.3Vdc ± 10%
732.4Hz — 85MHz
L (*)
Operating temp. (Topr)
F and Vdd dependent
3 mA max. at 5V up to 5MHz
25 mA max. at 15V up to 15MHz
See Option codes
-62ºC to + 125ºC
See Option codes
0.045Hz ~ < 16MHz
16MHz ~ < 40MHz
40MHz ~ < 60MHz
60MHz ~
85MHz
45/55% max. Fo < 12MHz
40/60% max. Fo ≥ 12MHz
3 mA max. - 0.045Hz ~ < 500kHz
6 mA max. - 500kHz ~ < 16MHz
10 mA max. - 16MHz ~ < 32MHz
20 mA max. - 32MHz ~ < 60MHz
30 mA max. - 60MHz ~ < 100MHz
40 mA max. - 100MHz ~ 125MHz
Operating supply current
(Idd) (No Load)
Symmetry
(50% of ouput waveform or 1.4Vdc for
TTL)
Rise and Fall times
(with typical load)
Output Load
Start-up time (Tstup)
Output voltage (Voh/Vol)
Output Current (Ioh/Iol)
Enable/Disable
Tristate function Pin 1
Aging (at 70ºC)
20 mA max. -
25 mA max. -
35 mA max. -
45 mA max. -
45/55% max. Fo < 4MHz
40/60% max. Fo ≥ 4MHz
30ns max.
(Measured from 10% to 90%)
15pF // 10kΩ
15ns max. Fo < 15kHz
6ns max. Fo 15kHz ~ 39.999MHz
3ns max. Fo 40MHz ~ 125 MHz
(Measured from 10% to 90% CMOS or from 0.8V to 2.0V TTL)
10TTL Fo < 20MHz
6TTL Fo ≥ 20MHz
15pF // 10kΩ
10ms max.
0.9 x Vdd min.; 0.1 x Vdd max.
± 24mA
± 1mA typ. at 5V
± 6.8mA typ. at 15V
±8 mA
VIH ≥ 2.2V Oscillation;
VIL ≤ 0.8V High Impedance
2.4V min.; 0.4V max.
-1.6mA / TTL
+40µA / TTL
0.9 x Vdd min.; 0.1 x Vdd max.
± 4mA .
Call for details
Jitter RMS 1σ (at 25ºC)
8ps typ. - < 40MHz
5ps typ. - ≥ 40MHz
VIH ≥ 0.7 x Vdd Oscillation;
VIL ≤ 0.3 x Vdd High Impedance
15ps typ. - < 40MHz
8ps typ. - ≥ 40MHz
(*)
Z
Available in 2.5Vdc (N) or 1.8Vdc (R)
Output logic can drive up to 200 pF load with typical 6ns rise & fall times (tr, tf)
ECL, PECL, LVPECL are available. Please contact Q-Tech for details.
Q-TECH Corporation
-
± 5ppm max. first year / ± 2ppm typ. per year thereafter
10150 W. Jefferson Boulevard, Culver City 90232
-
Tel: 310-836-7900 - Fax: 310-836-2157
-
www.q-t ec h.c om
Transistor Outline Packages (Revision A, May 2008) (ECO# 9304)
2
TRANSISTOR OUTLINE PACKAGES
Q-TECH
Package Configuration Versus Pin Connections
A
B
CORPORATION
TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS
1.8 to 15Vdc - 0.045Hz to 125MHz
QT1
QT2
Q-TECH
P/N
FREQ.
D/C S/N
QT3
Q-TECH
P/N
FREQ.
D/C S/N
C
QT14
D
Q-TECH
P/N
FREQ.
D/C S/N
Q-TECH
P/N
FREQ.
D/C S/N
.260
(6.60)
.300
MAX.
.200
MAX.
(5.08)
(7.62)
MAX.
.175
(4.45)
.500
(12.70)
MIN.
.500
MIN.
(12.70)
.500
(12.70)
MIN.
.500 MIN.
(12.70)
.018
(.457)
.360
(9.14)
.018
(.457)
.018
(.457)
.540
.018
(.457)
.360
(9.14)
.500
(12.70)
PIN No. 1
PIN No. 1
(13.72)
PIN No. 1
PIN No. 1
.200
(5.08)
.300
(7.62)
.282
(7.16)
.200
(5.08)
.075
(1.91)
Dimensions are in inches (mm)
QT #
QT1
QT2
QT3
QT14
Conf Vcc GND
A
B
C
D
8
12
8
8
4
6
4
4
Case
4
6
4
4
Output E/D
5
5
5
5
1
3
1
1
Ext. Cap
1&2
9 & 10
1&2
1&2
Equivalent
MIL-PRF-55310
Configuration
/09 = QT1T
/12 = QT1C
/10 = QT3T
/13 = QT3C
N/A
N/A
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-t ec h.com
Transistor Outline Packages (Revision A, May 2008) (ECO# 9304)
3
TRANSISTOR OUTLINE PACKAGES
Q-TECH
Test Circuit
CORPORATION
Output Waveform (Typical)
SYMMETRY =
TYPICAL TEST CIRCUIT FOR QT1T3 (10TTL)
+5VDC
0.01uF
OUTPUT
270
TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS
1.8 to 15Vdc - 0.045Hz to 125MHz
TH
T
x 100%
Tr
VOH
Tf
Vdd
0.9xVdd
8
5
QT1T3
6k
1
2
4
D1
D2
0.5xVdd
20pF(*)
D3
D4
GND
0.1xVdd
VOL
TH
GND
Cext
D1-D4: 1N4148 or equivalent
(*) CL includes scope probe capacitance
Typical test circuit for TTL logic.
Vdd
RL
Startup Time
Oscilloscope
54616B Agilent
Variable Ramp
T
TYPICAL SET-UP FOR START-UP TIME
+
-
+
Vdc
-
0.1µF
or
0.01µF
mA
+
POWER
SUPPLY
-
Vdd OUT
OUT
E/D GND
CL
Rs
DUT
LOAD
6 TTL
10 TTL
CL(*)
12pF
20pF
RL
430Ω
270Ω
RS
10kΩ
6kΩ
Ts
Start-up box
(*) CL inclides the loading effect of the oscilloscope probe.
Typical test circuit for CMOS logic
Supply Current
TYPICAL SUPPLY CURRENT ICC (mA) AT 3.3Vdc & 5.0Vdc CMOS Logic NO LOAD
+ mA
+
Power
supply
-
+
Vdc
Vdd Out
0.1µF
or
E/D GND
0.01µF
Output
45
40
35
30
Icc (mA)
-
15pF
(*)
10k
Ground
25
20
15
10
Tristate Function
5
0
0.5 2
8
16 24 27 32 36 40 48 50 55 65 70 75 85 100 125 133 150 160
Freq(MHz)
Icc 3.3V
Icc 5V
The Tristate function on pin 1 has a built-in pull-up resistor typical 50kΩ, so it
can be left floating or tied to Vdd without deteriorating the electrical performance.
(*) CL includes probe and jig capacitance
Frequency vs. Temperature Curve
40
30
20
Frequency Stability (PPM)
10
0
-10
-20
-30
-40
-50
-55
FREQUENCY STABILITY VERSUS TEMPERATURE QT1L -36MHz
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100 105 110 115 120 125
Temperature (°C)
SN2
SN3
SN4
SN1
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-t ec h.com
Transistor Outline Packages (Revision A, May 2008) (ECO# 9304)
4
TRANSISTOR OUTLINE PACKAGES
Q-TECH
Thermal Characteristics
CORPORATION
TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS
1.8 to 15Vdc - 0.045Hz to 125MHz
The heat transfer model in a hybrid package is described in
figure 1.
D/A epoxy
Die
D/A epoxy
45º
Heat
Hybrid Case
45º
Substrate
Heat spreading occurs when heat flows into a material layer of
increased cross-sectional area. It is adequate to assume that
spreading occurs at a 45° angle.
The total thermal resistance is calculated by summing the
thermal resistances of each material in the thermal path
between the device and hybrid case.
RT = R1 + R2 + R3 + R4 + R5
R1
R2
R3
R4
R5
Die
D/A epoxy
The total thermal resistance RT (see figure 2) between the heat
source (die) to the hybrid case is the Theta Junction to Case
(Theta JC) in°C/W.
(Figure 1)
Substrate
D/A epoxy
Hybrid Case
T
CA
• Theta junction to case (Theta JC) for this product is 30°C/W.
• Theta case to ambient (Theta CA) for this part is 100°C/W.
• Theta Junction to ambient (Theta JA) is 130°C/W.
Maximum power dissipation PD for this package at 25°C is:
• PD(max) = (TJ (max) – TA)/Theta JA
• With TJ = 175°C (Maximum junction temperature of die)
• PD(max) = (175 – 25)/130 = 1.15W
A
T
C
JC
T
J
Die
JC
CA
JA
(Figure 2)
Environmental Specifications
Q-Tech Standard Screening/QCI (MIL-PRF55310) is available for all of our Transistor Outline packages. Q-Tech can also customize
screening and test procedures to meet your specific requirements. The Transistor Outline packages are designed and processed to
exceed the following test conditions:
Environmental Test
Temperature cycling
Constant acceleration
Seal Fine Leak
Burn-in
Aging
Vibration sinusoidal
Shock, non operating
Thermal shock, non operating
Ambient pressure, non operating
Resistance to solder heat
Moisture resistance
Terminal strength
Resistance to solvents
Solderability
Test Conditions
MIL-STD-883, Method 1010, Cond. B
MIL-STD-883, Method 2001, Cond. A, Y1
MIL-STD-883, Method 1014, Cond. A
160 hours, 125°C with load
30 days, 70°C
MIL-STD-202, Method 204, Cond. D
MIL-STD-202, Method 213, Cond. I
MIL-STD-202, Method 107, Cond. B
MIL-STD-202, 105, Cond. C, 5 minutes dwell time minimum
MIL-STD-202, Method 210, Cond. C
MIL-STD-202, Method 106
MIL-STD-202, Method 211, Cond. C
MIL-STD-202, Method 215
MIL-STD-202, Method 208
Please contact Q-Tech for higher shock requirements
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-t ec h.com
Transistor Outline Packages (Revision A, May 2008) (ECO# 9304)
5
Analogue and Mixed Signal
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