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MPC8360TZUALFGA: DescriptionPowerQUICC⑩ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications; File Size1MB，112 Pages; ManufacturerFREESCALE (NXP)

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MPC8360TZUALFGA Overview

PowerQUICC⑩ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications

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Freescale Semiconductor

Technical Data

Document Number: MPC8360EEC

Rev. 2, 12/2007

MPC8360E/MPC8358E

PowerQUICC™ II Pro Processor

Revision 2.x TBGA Silicon

Hardware Specifications

This document provides an overview of the MPC8360E/58E

PowerQUICC

™

II Pro processor revision 2.x TBGA

features, including a block diagram showing the major

functional components. This device is a cost-effective,

highly integrated communications processor that addresses

the needs of the networking, wireless infrastructure and

telecommunications markets. Target applications include

next generation DSLAMs, network interface cards for 3G

basestations (Node Bs), routers, media gateways and high

end IADs. The device extends current PowerQUICC II Pro

offerings, adding higher CPU performance, additional

functionality, faster interfaces and robust interworking

between protocols while addressing the requirements related

to time-to-market, price, power, and package size. This

device can be used for the control plane along with data

plane functionality.

For functional characteristics of the processor, refer to the

MPC8360E Integrated Communications Processor Family

Reference Manual, Rev. 2.

To locate any published errata or updates for this document,

contact your Freescale sales office.

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Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13

Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16

DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 19

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

UCC Ethernet Controller: Three-Speed Ethernet, MII

Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

HDLC, BISYNC, Transparent, and Synchronous

UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . 68

Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

System Design Information . . . . . . . . . . . . . . . . . . . 104

Document Revision History. . . . . . . . . . . . . . . . . . . 108

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 108

Overview

•

– Asynchronous HDLC

– UART

– BISYNC up to 2 Mbps

– User-programmable Virtual FIFO size

– QUICC Multichannel Controller (QMC) for 64 TDM channels

— One multichannel communication controller (MCC) only on the MPC8360E supporting the

following:

– 256 HDLC or transparent channels

– 128 SS7 channels

– Almost any combination of subgroups can be multiplexed to single or multiple TDM

interfaces

— Two UTOPIA/POS interfaces on the MPC8360E supporting 124 MultiPHY each (optional

2*128 MultiPHY with extended address) and one UTOPIA/POS interface on the MPC8358E

supporting 31/124 MultiPHY

— Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management

— Eight TDM interfaces on the MPC8360E and four TDM interfaces on the MPC8358E with

1-bit mode for E3/T3 rates in clear channel

— Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC

and MCC serial channels (MCC is only available on the MPC8360E)

— Four independent 16-bit timers that can be interconnected as four 32-bit timers

— Interworking functionality:

– Layer 2 10/100-Base T Ethernet switch

– ATM-to-ATM switching (AAL0, 2, 5)

– Ethernet-to-ATM switching with L3/L4 support

– PPP interworking

Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,

802.11i, iSCSI, and IKE processing. The security engine contains four crypto-channels, a

controller, and a set of crypto execution units (EUs).

— Public key execution unit (PKEU) supporting the following:

– RSA and Diffie-Hellman

– Programmable field size up to 2048 bits

– Elliptic curve cryptography

– F2m and F(p) modes

– Programmable field size up to 511 bits

— Data encryption standard execution unit (DEU)

– DES, 3DES

– Two key (K1, K2) or three key (K1, K2, K3)

– ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2

Freescale Semiconductor

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