Integrated
Circuit
Systems, Inc.
ICS95V842
DDR Phase Lock Loop Clock Driver (60MHz - 220MHz)
Recommended Application:
1:2 DDRI Clock Driver
Product Description/Features:
• Low skew, low jitter PLL clock driver
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• With bypass mode mux
• Operating frequency 60 to 220 MHz
Switching Characteristics:
• CYCLE - CYCLE jitter: <75ps
• OUTPUT - OUTPUT skew: <60ps
• Period jitter: ±75ps
• Half-Period jitter: ±75ps
Pin Configuration
VDD2.5
DDRT0
DDRC0
GND
CLK_INT
CLK_INC
AVDD
AGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
DDRC1
DDRT1
VDD2.5
FB_INC
FB_INT
FB_OUTT
FB_OUTC
16 pin SSOP
Functionality
INPUTS
GND
GND
2.5V
(nom)
2.5V
(nom)
L
H
L
H
H
L
H
L
L
H
L
H
H
L
H
L
OUTPUTS
L
H
L
H
H
L
H
L
AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
PLL State
Bypassed/Off
Bypassed/Off
On
On
Block Diagram
FB_INT
FB_INC
CLK_INC
CLK_INT
PLL
FB_OUTT
FB_OUTC
DDRT (1:0)
DDRC (1:0)
AVDD
0830A—09/10/04
ICS95V842
ICS95V842
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
2
3
4
5
6
7
8
9
VDD2.5
DDRT0
DDRC0
GND
CLK_INT
CLK_INC
AVDD
AGND
FB_OUTC
PWR
OUT
OUT
PWR
IN
IN
PWR
PWR
OUT
10
FB_OUTT
OUT
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
"True" reference clock input.
"Complementary" reference clock input.
3.3V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
Complement single-ended feedback output, dedicated external
feedback. It switches at the same frequency as other DDR outputs,
This output must be connect to FB_INC.
True single-ended feedback output, dedicated external feedback. It
switches at the same frequency as other DDR outputs, This output
must be connect to FB_INT.
True single-ended feedback input, provides feedback signal to internal
PLL for synchronization with CLK_INT to eliminate phase error.
Complement single-ended feedback input, provides feedback signal to
internal PLL for synchronization with CLK_INT to eliminate phase
error.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
11
FB_INT
IN
12
13
14
15
16
FB_INC
VDD2.5
DDRT1
DDRC1
GND
IN
PWR
OUT
OUT
PWR
0830A—09/10/04
2
ICS95V842
Absolute Maximum Ratings
Supply Voltage: (VDD & AVDD) . . . . . . . . . . . . . . . . -0.5V to 3.6V
Input clamp current: I
IK
(VI < 0 or VI > VDD) . . . . . . +/- 50mA
Output clamp current: I
OK
(VO < 0 or VO > VDD) . . +/- 50mA
Continuous output current: I
O
(VO = 0 to VDD) . . . . +/- 50mA
Package thermal impedance, theta JA: DGG package +89°C/Ω
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
SYMBOL
MIN
TYP
PARAMETER
CONDITIONS
V
I
= V
DD
or GND
I
IH
5
Input High Current
V
I
= V
DD
or GND
I
IL
Input Low Current
I
DD2.5
C
L
= 0pF, R
L
=
∞Ω
Operating Supply
Current
I
DDPD
C
L
= 0pF, R
L
=
∞
Ω
Output High Current
Output Low Current
High Impedance
Output Current
Input Clamp Voltage
I
OH
I
OL
I
OZ
V
IK
V
OH
V
DD
= 2.3V, V
OUT
= 1V
V
DD
= 2.3V, V
OUT
= 1.2V
V
DD
=2.7V, Vout=V
DD
or GND
Iin = -18mA
V
DD
= min to max,
I
OH
= -1 mA
V
DD
= 2.3V,
I
OH
= -12 mA
V
DD
= min to max
I
OL
=1 mA
V
DD
= 2.3V
I
OH
=12 mA
VI = V
DD
or GND
VI = V
DD
or GND
-18
26
±10
-1.2
V
DD
- 0.1
1.7
0.1
0.6
3
3
V
pF
pF
MAX
5
160
100
UNITS
µA
µA
mA
µA
mA
mA
µA
V
V
V
High-level output voltage
Low-level output voltage
V
OL
C
IN
Input Capacitance
1
C
OUT
Output Capacitance
1
1
Guaranteed by design and characterization, not 100% tested in production.
0830A—09/10/04
3
ICS95V842
DC Electrical Characteristics
TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Supply Voltage
V
DDQ
, A
VDD
2.3
2.5
CLK_INT, CLK_INC, FB_INC,
Low level input voltage
V
IL
0.4
FB_INT
CLK_INT, CLK_INC, FB_INC,
V
DD
/2 + 0.18
2.1
High level input voltage
V
IH
FB_INT
DC input signal voltage
V
IN
-0.3
(note 1,2)
Differential input signal
CLK_INT, CLK_INC, FB_INC,
V
ID
0.36
voltage (note 3)
FB_INT
Differential output voltage
CLK_INT, CLK_INC, FB_INC,
V
OD
0.7
(note 3)
FB_INT
Output differential cross-
V
OX
V
DD
/2 - 0.15
voltage (note 4)
Input differential cross-
V
DD
/2 - 0.2 V
DD
/2
V
IX
voltage (note 4)
Operating free-air
T
A
0
temperature
MAX
2.7
V
DD
/2 - 0.18
UNITS
V
V
V
V
DD
+ 0.3
V
DD
+ 0.6
V
DD
+ 0.6
V
DD
/2 + 0.15
V
DD
/2 + 0.2
85
V
V
V
V
V
°C
Notes:
1 Unused inputs must be held high or low to prevent them from floating.
2 DC input signal voltage specifies the allowable DC excursion of differential input.
3 Differential input signal voltage specifies the differential voltage [VTR-VCP] required for switching,
where VTR is the true input level and VCP is the complementary input level.
4 Differential cross-point voltage is expected to track variations of VDD and is the voltage at which
the differential signal must be crossing.
Timing Requirements
T
A
= 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
CONDITIONS
PARAMETER
SYMBOL
MIN
MAX UNITS
Max clock frequency
3
Application Frequency
Range
3
Input clock duty cycle
CLK stabilization
freq
op
freq
App
d
tin
T
STAB
33
60
40
233
220
60
100
MHz
MHz
%
µs
0830A—09/10/04
4
ICS95V842
Switching Characteristics
T
A
= 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
CONDITION
SYMBOL
MIN
TYP
freq
op
40
Max clock frequency
3
Application Frequency
freq
App
60
Range
3
d
tin
Input clock duty cycle
40
t
sl(I)
1
Input clock slew rate
T
STAB
CLK stabilization
Low-to high level propagation
CLK_IN to any output
t
PLH1
delay time
High-to low level propagation
CLK_IN to any output
t
PHL1
delay time
t
en
Output enable time
PD# to any output
5
t
dis
PD# to any output
5
Output disable time
t
jit (per)
-75
Period jitter
t
jit(hper)
-75
Half-period jitter
t
sl(o)
Over the application
1
Output clock slew rate
frequency range
t
cyc
-t
cyc
-75
Cycle to Cycle Jitter
t
(spo)
-50
Static Phase Offset
t
skew
Output to Output Skew
40
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,
were the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics are guaranteed for application frequency range. The
PLL Locks over the Max Clock Frequency range, but the device doe not
necessarily meet other timing parameters.
4. Does not include jitter.
MAX
333
220
60
2
100
5.5
5.5
UNITS
MHz
MHz
%
v/ns
µs
ns
ns
ns
ns
ps
ps
v/ns
ps
ps
ps
75
75
2.5
75
50
60
0830A—09/10/04
5
京公网安备 11010802033920号
EEWORLD
