MC803256K32, MC803256K36
M
O
S
YS
256Kx32/36 Pipeline Burst RAM
®
Ultra low power for green PC and battery
powered PC
•
High Performance
133-166MHz Speed grades
3-1-1-1 Burst Read
1-1-1-1 Burst Write
3-1-1-1-1-1-1-1... pipeline operation
•
Low Power
Low active power
Ultra low power ZZ standby mode
Single 3.3V supply (V
DD
)
Isolated 3.3V or 2.5V I/O supply (V
DDQ
)
•
Compatibility
Individual Byte Write and Global Write mask-
ing
Interleave and burst address support
Industry standard 100-Pin PBSRAM pinout
Industry standard PBSRAM specification
•
Applications
Processor L2 Cache
Ideal for high speed, low power communica-
tions buffers
Power sensitive portable DSP applications
______________________________________________
LBO#
A5
A4
A3
A2
A1
A0
NC
NC
Figure 1. Pin Function
Overview
The MoSys MC803256K is a high performance, low
power pipeline-burst-SRAM (PBSRAM). Fabricated using
an advanced low power, high performance CMOS proc-
ess, the MoSys MC803256K is backward pin and func-
tion compatible with standard 32Kx32/36, 64Kx32/36
and 128Kx32/36 PBSRAMs with additional operating
features like low power ZZ standby mode and linear
burst order addressing. These additional operating fea-
tures are defined so that, with proper implementation,
PC boards can work transparently with 32Kx32/36,
64Kx32/36, 128Kx32/36 or 256Kx32/36 configurations,
allowing the designer maximum configuration flexibility
within a single footprint layout.
The MoSys MC803256K supports PBSRAM operating
modes at maximum burst frequency including indefinite
pipeline read or write (3-1-1-1-1-1-1...)
Parameter
Cycle Time
Access Time
Clock to High-Z
Symbol
tKC
tKQ
tKQHZ
-7R5
7.5
4.5
4
-6
6
3.5
3.4
Unit
ns
ns
ns
Available in 256Kx32 and 256Kx36 bit densities, the
MoSys MC803256K is packaged in a standard 100 lead
LQFP.
Lowest Power
The MC803256K affords systems dramatic power sav-
ings due to the benefits of its proprietary MoSys tech-
nology. Peak operating power of a typical PBSRAM is
5x that of the MC803256K. Making it ideal for portable
applications, as well as applications requiring a large
amount of RAM.
Part Number Designation
Example:
MC803256K32L-7R5 I
Device Designation:
MC8:,
Series:
03
Organization:
256K32 - 256Kx32 SCD
256D32 - 256Kx32 DCD
Package Type: L=LQFP
Speed: – 7R5 133MHz
–6
166MHz
Temp:
I
= Industrial Temperature
DS12, Rev 1.7 – 01/26/01
Preliminary Information
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC, (DQP3)
DQ17
DQ18
VDDQ
VSSQ
DQ19
DQ20
DQ21
DQ22
VSSQ
VDDQ
DQ23
DQ24
NC
VDD
NC
VSS
DQ25
DQ26
VDDQ
VSSQ
DQ27
DQ28
DQ29
DQ30
VSSQ
VDDQ
DQ31
DQ32
NC, (DQP4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A6
A7
CE1#
CE2
BW4#
BW3#
BW2#
BW1#
A17
VDD
VSS
CLK
GW#
BWE#
OE#
ADSC#
ADSP#
ADV#
A8
A9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
•
High performance, low power pipeline burst SRAM
100 Pin LQFP
100 Pin PQFP
20 mm x 14 mm body
0.65 mm nominal pin pitch
NC, (DQP2)
DQ16
DQ15
VDDQ
VSSQ
DQ14
DQ13
DQ12
DQ11
VSSQ
VDDQ
DQ10
DQ9
VSS
NC
VDD
ZZ
DQ8
DQ7
VDDQ
VSSQ
DQ6
DQ5
DQ4
DQ3
VSSQ
VDDQ
DQ2
DQ1
NC, (DQP1)
Page 1
© 2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
MC803256K32, MC803256K36
M
O
S
YS
256Kx32/36 Pipeline Burst RAM
®
LBO#
CLK
ADV#
ADSC#
ADSP#
A[17:0]
Binary
Counter
CLK
CKE# Q1
CLR
18
D
Q
Address
Register
CKE#
CLK
16
18
256K x 32/36
Memory
Array
GW#
BWE#
BW4#
D
Q
DQ[32:2
ByteWrite
Registers
CL
32/36
32/36
D
Q
BW3#
DQ[24:17]
ByteWrite
Registers
CL
D
Q
BW2#
DQ[16:9
ByteWrite
Registers
CLK
BW1#
D
Q
DQ[8:1]
ByteWrite
Registers
CLK
CE1#
CE2
D
Q
Enable
Register
CKE#
CLK
D
Q
Enable
Delay
Register
CL
4
Vdd
DCD
SCD
Output
Register
Input
Register
OE
OE#
32/36
DATA[32/36:1]
Figure 2 Functional Block Diagram
DS12, Rev 1.7 – 01/26/01
Preliminary Information
Page 2
© 2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
MC803256K32, MC803256K36
M
O
S
YS
256Kx32/36 Pipeline Burst RAM
®
Table 1. LQFP Pin Description
Pin Number
92, 50, 49, 48, 47, 46, 45, 44, 81, 82,
99, 100, 32, 33, 34, 35, 36 ,37
96,95, 94, 93
88
87
89
98
97
86
83
84
85
64
31
29, 28, 25, 24, 23, 22, 19, 18, 13, 12, 9,
8, 7, 6, 3, 2, 79, 78, 75, 74, 73, 72, 69,
68, 63, 62, 59, 58, 57, 56, 53, 52
30, 1, 80, 51
14, 16, 38, 39, 42, 43, 66
15, 41, 65, 91
17, 40, 67, 90
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
Symbol
A[17:0]
BW[4:1]#
GW#
BWE#
CLK
CE1#
CE2
OE#
ADV#
ADSP#
ADSC#
ZZ
LBO#
DQ[32:1]
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Description
Processor Addresses
Processor host bus byte enables.
Global Write from cache controller
Byte Write Enable from controller
Processor host bus clock
ADSP# mask and ADSC# chip enable
Depth expansion chip enable
Asynchronous output enable
Burst address counter advance
ADS# of processor
ADS# of controller
Low power sleep mode
Linear Burst Order
Data I/O pins
NC/DQP[4:1]
NC
VDD
VSS
VDDQ
VSSQ
I/O
-
3.3 Volts
Ground
I/O Sup-
ply
I/O
Ground
Data parity I/O pins
unused
Power
Ground
I/O Buffer Supply
I/O Buffer Ground
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
DDQ
Vih
Vil
Ts
Parameter
Core Supply Voltage
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Storage Temperature
V
SSQ
-0.5
-65
150
Min
Max
4.0
V
DDQ
V
DD
+0.5,
V
DDQ
4.0
V
DDQ
+0.5
Units
V
V
V
V
°C
Notes:
Max Vih is not to exceed maximum VDDQ
DS12, Rev 1.7 – 01/26/01
Preliminary Information
Page 3
© 2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
MC803256K32, MC803256K36
M
O
S
YS
256Kx32/36 Pipeline Burst RAM
®
Table 3. Recommended Operating Conditions
Symbol
VDD
VDDQ
Vih
Vil
Voh
Vol
TAC
TAI
Parameter
Supply Voltage
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Commercial Operating Temp.
Industrial Operating Temp.
Ioh = -5 mA
Iol = 5 mA
Condition
3.3V ±5%
2.5V +38%/-5%
Min
3.135
2.375
1.8
-0.3
2.4
0.4
0
-40
70
85
Max
3.465
3.465
V
DDQ
+ .3
0.8
Units
V
V
V
V
V
V
°
C
°
C
Table 4. Absolute Maximum AC Operating Conditions
Symbol
Vih
Vil
tOVR
tSET
Parameter
Input High Voltage
Input Low Voltage
Overshoot/Undershoot Voltage Duration
Overshoot/Undershoot Settling Time
Min
1.8
V
SSQ
- 1.0
Max
V
DDQ
+1.0
0.8
0.2*tCY
0.8*tCY
Units
V
V
ns
ns
Table 5. Maximum DC Current Requirements
Symbol
I
DD
I
DD1
I
DDZ
Condition
Current
60
10
2
Units
mA
mA
mA
Operating current, device selected; all inputs < Vil or > Vih; cycle time > tKC
min, VDD= max, 0 pF load
Idle current, device selected; ADSP#, ADSC#, GW#, BW#s, ADV# and all other
inputs > 2.8 volts; cycle time > tKC min, VDD= max, 0 pF load
Sleep mode, clock stopped, all inputs > 2.8 v, VDD= max
Table 6. Pin Capacitance
Symbol
C
I
C
I/O
Input Pin Capacitance
I/O Pin Capacitance
Parameter
Max
4
6
Units
pF
pF
DS12, Rev 1.7 – 01/26/01
Preliminary Information
Page 4
© 2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
MC803256K32, MC803256K36
M
O
S
YS
256Kx32/36 Pipeline Burst RAM
®
Table 6. AC Timing Characteristics at Recommended Operating Conditions
-6
(166 MHz)
Sym
tAAH
tAAS
tADSH
tADSS
tAH
tAS
tCEH
tCES
tDH
tDS
tKC
tKH
tKL
tKQ
tKQHZ
tKQLZ
tKQX
tOELZ
tOEHZ
tOEQ
tOEQX
tWS
tWH
tZZs
tZZREC
Parameter
ADV# hold
ADV# setup
ADSx# hold
ADSx# setup
Address hold
Address setup
Chip Enable hold
Chip Enable setup
Write Data hold
Write Data setup
Clock cycle
Clock high
Clock low
Clock to output valid
Clock to output high-Z
Clock to output low-Z
Clock to output invalid
OE# to output low-Z
OE# to output high-Z
OE# to output valid
OE# to output invalid
GW#, BWx# setup
GW#, BWx# hold
ZZ standby
ZZ recovery
100
0
1.5
0.5
100
100
1.5
0
1.5
0
3.8
3.8
0
2
0.5
100
Min
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
6
1.5
1.5
3.5
3.4
1.5
0
1.5
0
4.5
4.5
Max
-7R5
(133 MHz)
Min
0.5
2
0.5
2
0.5
2
0.5
2
0.5
2
7.5
2
2
4.5
4
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS12, Rev 1.7 – 01/26/01
Preliminary Information
Page 5
© 2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
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