IS43DR81280C-25DBLA1 datasheet, PDF

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IS43DR81280C-25DBLA1: DescriptionDDR DRAM, 128MX8, 0.4ns, CMOS, PBGA60, 8 X 10.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TWBGA-60; Categorystorage storage; File Size981KB，49 Pages; ManufacturerIntegrated Silicon Solution ( ISSI ); Environmental Compliance

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IS43DR81280C-25DBLA1 Overview

DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA60, 8 X 10.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TWBGA-60

IS43DR81280C-25DBLA1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
package instruction	TFBGA, BGA60,9X11,32
Reach Compliance Code	compliant
ECCN code	EAR99
Is Samacsys	N
access mode	MULTI BANK PAGE BURST
Maximum access time	0.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	400 MHz
I/O type	COMMON
interleaved burst length	4,8
JESD-30 code	R-PBGA-B60
length	10.5 mm
memory density	1073741824 bit
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	60
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA60,9X11,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Filter level	AEC-Q100
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	4,8
Maximum slew rate	0.3 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	8 mm
Base Number Matches	1

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IS43/46DR81280C

IS43/46DR16640C

128Mx8, 64Mx16 DDR2 DRAM

FEATURES

• V

= 1.8V ±0.1V, V

ddq

= 1.8V ±0.1V

• JEDEC standard 1.8V I/O (SSTL_18-compatible)

• Double data rate interface: two data transfers

per clock cycle

• Differential data strobe (DQS,

DQS)

• 4-bit prefetch architecture

• On chip DLL to align DQ and DQS transitions

with CK

• 8 internal banks for concurrent operation

• Programmable CAS latency (CL) 3, 4, 5, 6 and 7

supported

• Posted CAS and programmable additive latency

(AL) 0, 1, 2, 3, 4, 5 and 6 supported

• WRITE latency = READ latency - 1 tCK

• Programmable burst lengths: 4 or 8

• Adjustable data-output drive strength, full and

reduced strength options

• On-die termination (ODT)

DECEMBER 2015

DESCRIPTION

ISSI's 1Gb DDR2 SDRAM uses a double-data-rate

architecture to achieve high-speed operation. The

double-data rate architecture is essentially a 4n-prefetch

architecture, with an interface designed to transfer two

data words per clock cycle at the I/O balls.

ADDRESS TABLE

Parameter

Configuration

Refresh Count

Row Addressing

Column

Addressing

Bank Addressing

Precharge

Addressing

128M x 8

16M x 8 x 8

banks

8K/64ms

1K (A0-A9)

BA0 - BA2

A10

64M x 16

8M x 16 x 8

banks

8K/64ms

1K (A0-A9)

BA0 - BA2

A10

16K (A0-A13) 8K (A0-A12)

OPTIONS

• Configuration(s):

128Mx8 (16Mx8x8 banks): IS43/46DR81280C

64Mx16 (8Mx16x8 banks): IS43/46DR16640C

• Package:

x8: 60-ball BGA (8mm x 10.5mm)

x16: 84-ball WBGA (8mm x 12.5mm)

• Timing – Cycle time

2.5ns @CL=5 DDR2-800D

2.5ns @CL=6 DDR2-800E

3.0ns @CL=5 DDR2-667D

3.75ns @CL=4 DDR2-533C

5ns @CL=3 DDR2-400B

• Temperature Range:

Commercial (0°C

≤

85°C)

Industrial (-40°C

≤

95°C; -40°C

≤

85°C)

Automotive, A1 (-40°C

≤

95°C; -40°C

≤

85°C)

Automotive, A2 (-40°C

≤

Tc; T

≤

105°C)

KEY TIMING PARAMETERS

Speed Grade

tRCD

tRP

tRC

tRAS

tCK @CL=3

tCK @CL=4

tCK @CL=5

tCK @CL=6

-25D

12.5

3.75

2.5

-3D

3.75

—

Tc = Case Temp, T

= Ambient Temp

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest

version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-

ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications

unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com

Rev. A

12/3/2015

IS43DR81280C-25DBLA1 Related Products

	IS43DR81280C-25DBLA1	IS43DR16640C-25DBLA2	IS43DR16640C-25DBLA1	IS43DR16640C-3DBLA1	IS43DR16640C-3DBLA2
Description	DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA60, 8 X 10.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TWBGA-60	DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TWBGA-84	DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TWBGA-84	DDR DRAM, 64MX16, 0.45ns, CMOS, PBGA84, 8 X 12.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TWBGA-84	DDR DRAM, 64MX16, 0.45ns, CMOS, PBGA84, 8 X 12.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TWBGA-84
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
package instruction	TFBGA, BGA60,9X11,32	TFBGA, BGA84,9X15,32	TFBGA, BGA84,9X15,32	TFBGA, BGA84,9X15,32	TFBGA, BGA84,9X15,32
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
Maximum access time	0.4 ns	0.4 ns	0.4 ns	0.45 ns	0.45 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	400 MHz	400 MHz	400 MHz	333 MHz	333 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON
interleaved burst length	4,8	4,8	4,8	4,8	4,8
JESD-30 code	R-PBGA-B60	R-PBGA-B84	R-PBGA-B84	R-PBGA-B84	R-PBGA-B84
length	10.5 mm	12.5 mm	12.5 mm	12.5 mm	12.5 mm
memory density	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	8	16	16	16	16
Number of functions	1	1	1	1	1
Number of ports	1	1	1	1	1
Number of terminals	60	84	84	84	84
word count	134217728 words	67108864 words	67108864 words	67108864 words	67108864 words
character code	128000000	64000000	64000000	64000000	64000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	105 °C	85 °C	85 °C	105 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
organize	128MX8	64MX16	64MX16	64MX16	64MX16
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
Encapsulate equivalent code	BGA60,9X11,32	BGA84,9X15,32	BGA84,9X15,32	BGA84,9X15,32	BGA84,9X15,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
power supply	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	8192
Filter level	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES	YES
Continuous burst length	4,8	4,8	4,8	4,8	4,8
Maximum slew rate	0.3 mA	0.28 mA	0.28 mA	0.27 mA	0.27 mA
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	8 mm	8 mm	8 mm	8 mm	8 mm
Maker	-	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )
Maximum standby current	-	0.025 A	0.025 A	0.025 A	0.025 A

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