24C04A
4K 5.0V I
2
C
™
Serial EEPROM
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Low power CMOS technology
Hardware write protect
Two wire serial interface bus, I
2
C™ compatible
5.0V only operation
Self-timed write cycle (including auto-erase)
Page-write buffer
1 ms write cycle time for single byte
1,000,000 Erase/Write cycles guaranteed
Data retention >200 years
8-pin DIP/SOIC packages
Available for extended temperature ranges
- Commercial (C):
0˚C to +70˚C
- Industrial (I):
-40˚C to +85˚C
- Automotive (E):
-40˚C to +125˚C
PACKAGE TYPES
DIP
A0
A1
A2
V
SS
8-lead
SOIC
1
2
3
4
24C04A
8
7
6
5
V
CC
WP
SCL
SDA
A0
A1
A2
V
SS
1
2
3
4
24C04A
8
7
6
5
V
CC
WP
SCL
SDA
DESCRIPTION
The Microchip Technology Inc. 24C04A is a 4K bit
Electrically Erasable PROM. The device is organized
as with a standard two wire serial interface. Advanced
CMOS technology allows a significant reduction in
power over NMOS serial devices. A special feature
provides hardware write protection for the upper half of
the block. The 24C04A has a page write capability of
up to eight bytes, and up to four 24C04A devices may
be connected to the same two wire bus.
This device offers fast (1ms) byte write and
extended (-40
°
C to 125
°
C) temperature operation.
It is recommended that all other applications use
Microchip’s 24LC04B.
14-lead
SOIC
NC
A0
A1
NC
A2
Vss
NC
1
2
24C04A
3
4
5
6
7
14
13
12
11
10
9
8
NC
Vcc
WP
NC
SCL
SDA
NC
BLOCK DIAGRAM
Vcc
Vss
Data
Buffer
(FIFO)
Data Reg.
SDA
A
d
d
r
e
s
s
V
PP
R/W Amp
Slave Addr.
P
o
i
n A0 to
t A7
e
r
Increment
Memory
Array
SCL
Control
Logic
A8
A0 A1 A2 WP
I
2
C is a trademark of Philips Corporation.
©
1998 Microchip Technology Inc.
DS11183E-page 1
24C04A
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
A0
A1, A2
V
SS
SDA
SCL
WP
V
CC
PIN FUNCTION TABLE
Function
No Function - Must be connected to
V
CC
or V
SS
Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+5V Power Supply
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.6V to V
CC
+1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied................. -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins................................................4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
Commercial (C): Tamb = 0
°
C to +70
°
C
Industrial (I):
Tamb = -40
°
C to +85
°
C
Automotive (E): Tamb = -40
°
C to +125
°
C
Symbol
V
TH
V
IH
V
IL
V
OL
V
IH
V
IL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
Write
I
CC
Write
I
CC
Read
I
CCS
Min.
2.8
V
CC
x 0.7
-0.3
Max.
4.5
V
CC
+ 1
V
CC
x 0.3
0.4
V
CC
+ 0.5
0.5
10
10
7.0
3.5
4.25
750
100
Units
V
V
V
V
V
V
µ
A
µ
A
pF
mA
mA
µ
A
µ
A
Conditions
V
CC
= +5V (
±
10%)
Parameter
V
CC
detector threshold
SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage
A1 & A2 pins:
High level input voltage
Low level input voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Operating current
I
OL
= 3.2 mA (SDA only)
V
CC
- 0.5
-0.3
—
—
—
—
—
—
—
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
V
IN
/V
OUT
= 0V (Note)
Tamb = +25˚C, f = 1 MHz
F
CLK
= 100 kHz, program cycle time = 1 ms,
Vcc = 5V, Tamb = 0˚C to +70˚C
F
CLK
= 100 kHz, program cycle time = 1 ms,
Vcc = 5V, Tamb = (I) and (E)
V
CC
= 5V, Tamb= (C), (I) and (E)
SDA=SCL=V
CC
=5V (no PROGRAM active)
WP/TEST = V
SS
, A0, A1, A2 = V
SS
Standby current
Note: This parameter is periodically sampled and not 100% tested
FIGURE 1-1:
BUS TIMING START/STOP
V
HYS
SCL
T
SU
:
STA
SDA
T
HD
:
STA
T
SU
:
STO
START
STOP
DS11183E-page 2
©
1998 Microchip Technology Inc.
24C04A
TABLE 1-3:
AC CHARACTERISTICS
Symbol
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:S
TA
T
SU
:S
TA
T
HD
:D
AT
T
SU
:D
AT
T
AA
T
SU
:S
TO
T
BUF
Min.
—
4000
4700
—
—
4000
4700
0
250
300
4700
4700
Typ
—
—
—
—
—
—
—
—
—
—
—
—
Max.
100
—
—
1000
300
—
—
—
—
3500
—
—
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
ns
ns
Time the bus must be free
before a new transmission
can start
Remarks
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
Data output delay time
STOP condition setup time
Bus free time
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
Byte mode
Page mode, N=# of bytes
Endurance
—
1M
25
°
C, Vcc = 5.0V, Block
Mode (Note 2)
Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
Input filter time constant
(SDA and SCL pins)
Program cycle time
T
I
T
WC
—
—
—
.4
.4N
—
100
1
N
—
ns
ms
ms
cycles
FIGURE 1-2:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
SCL
T
SU
:
STA
T
HD
:
STA
SDA
IN
T
HD
:
DAT
T
SP
T
AA
T
SU
:
DAT
T
SU
:
STO
T
AA
SDA
OUT
T
HD
:
STA
T
BUF
©
1998 Microchip Technology Inc.
DS11183E-page 3
24C04A
2.0
FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24C04A supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be con-
trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions, while the 24C04A
works as slave. Both master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
Up to four 24C04As can be connected to the bus,
selected by A1 and A2 chip address inputs. A0 must
be tied to V
CC
or V
SS
.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
3.5
Acknowledge
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24C04A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1:
SCL
(A)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
(D)
(C)
(A)
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
DS11183E-page 4
©
1998 Microchip Technology Inc.
24C04A
4.0
SLAVE ADDRESS
5.0
BYTE PROGRAM MODE
The chip address inputs A1 and A2 must be externally
connected to either V
CC
or ground (V
SS
), thereby
assigning a unique address to each device. A0 is not
used on the 24C04A and must be connected to either
V
CC
or V
SS
. Up to four 24C04A devices may be con-
nected to the bus. Chip selection is then accomplished
through software by setting the bits A1 and A2 of the
slave address to the corresponding hard-wired logic lev-
els of the selected 24C04A. After generating a START
condition, the bus master transmits the slave address
consisting of a 4-bit device code (1010), followed by the
chip address bits A0, A1 and A2. The seventh bit of that
byte (A0) is used to select the upper block (addresses
100—1FF) or the lower block (addresses 000—0FF) of
the array.
The eighth bit of the slave address determines if the
master device wants to read or write to the 24C04A
(Figure 4-1).
The 24C04A monitors the bus for its corresponding
slave address all the time. It generates an acknowl-
edge bit if the slave address was true and it is not in a
programming mode.
In this mode, the master sends addresses and one
data byte to the 24C04A.
Following the START signal from the master, the device
code (4-bits), the slave address (3-bits), and the R/W
bit, which is logic LOW, are placed onto the bus by the
master. This indicates to the addressed 24C04A that a
byte with a word address will follow after it has gener-
ated an acknowledge bit. Therefore the next byte trans-
mitted by the master is the word address and will be
written into the address pointer of the 24C04A. After
receiving the acknowledge, the master device trans-
mits the data word to be written into the addressed
memory location. The 24C04A acknowledges again
and the master generates a STOP condition. This ini-
tiates the internal programming cycle (Figure 6-1).
FIGURE 4-1:
START
SLAVE ADDRESS
ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
A2
A1
A0
©
1998 Microchip Technology Inc.
DS11183E-page 5
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