P4C1256L-45CMBLF datasheet, PDF

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P4C1256L-45CMBLF: DescriptionHIGH SPEED 32K x 8 STATIC CMOS RAM; Categorystorage storage; File Size172KB，17 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/; Environmental Compliance

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P4C1256L-45CMBLF Overview

HIGH SPEED 32K x 8 STATIC CMOS RAM

P4C1256L-45CMBLF Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	DIP
package instruction	DIP,
Contacts	28
Reach Compliance Code	compli
ECCN code	3A001.A.2.C
Is Samacsys	N
Maximum access time	45 ns
JESD-30 code	R-CDIP-T28
memory density	262144 bi
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	28
word count	32768 words
character code	32000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	32KX8
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Filter level	MIL-STD-883 Class B
Maximum seat height	5.715 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

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P4C1256

HIGH SPEED 32K x 8

STATIC CMOS RAM

FEATURES

High Speed (Equal Access and Cycle Times)

— 12/15/20/25/35 ns (Commercial)

— 15/20/25/35/45 ns (Industrial)

— 20/25/35/45/55/70 ns (Military)

Low Power

Single 5V±10% Power Supply

Easy Memory Expansion Using

and

Inputs

Common Data I/O

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Fast t

Automatic Power Down

Packages

—28-Pin 300 mil DIP, SOJ, TSOP

—28-Pin 300 mil Ceramic DIP

—28-Pin 600 mil Ceramic DIP

—28-Pin CERPACK

—28-Pin SOP

—28-Pin LCC (350 mil x 550 mil)

—32-Pin LCC (450 mil x 550 mil)

DESCRIPTION

The P4C1256 is a 262,144-bit high-speed CMOS

static RAM organized as 32Kx8. The CMOS memory

requires no clocks or refreshing, and has equal access

and cycle times. Inputs are fully TTL-compatible. The

RAM operates from a single 5V±10% tolerance power

supply.

Access times as fast as 12 nanoseconds permit greatly

enhanced system operating speeds. CMOS is utilized

to reduce power consumption to a low level. The

P4C1256 is a member of a family of PACE RAM™ prod-

ucts offering fast access times.

The P4C1256 device provides asynchronous operation

with matching access and cycle times. Memory loca-

tions are specified on address pins A

to A

. Reading

is accomplished by device selection (CE and output

enabling (OE) while write enable (WE) remains HIGH.

By presenting the address under these conditions, the

data in the addressed memory location is presented on

the data input/output pins. The input/output pins stay

in the HIGH Z state when either

is HIGH or

is LOW.

Package options for the P4C1256 include 28-pin 300

mil DIP, SOJ and TSOP packages. For military tempera-

ture range, Ceramic DIP and LCC packages are avail-

able.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

DIP (P5, C5, C5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3)

CERPACK (F4) SIMILAR

1519B

See end of datasheet for LCC and TSOP

pin configurations.

Document #

SRAM119

REV G

Revised June 2007

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