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TinyLogic UHS D-Type,
Flip-Flop with Preset and
Clear
NC7SZ74
Description
The NC7SZ74 is a single, D−type, CMOS flip−flop with preset and
clear from ON Semiconductor ultra high−speed series of TinyLogic.
The device is fabricated with advanced CMOS technology to achieve
ultra high speed with high output drive, while maintaining low static
power dissipation over a very broad V
CC
operating range of 1.65 V to
5.5 V V
CC
. The inputs and outputs are high impedance when V
CC
is
0 V. Inputs tolerate voltages up to 5.5 V, independent of V
CC
operating
voltage.
The signal level applied to the D input is transferred to the Q output
during the positive−going transition of the CLK pulse.
Features
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MARKING
DIAGRAMS
US8
CASE 846AN
SZ74
ALYW
•
•
•
•
•
•
Ultra−High Speed: t
PD
2.6 ns (Typical) into 50 pF at 5 V V
CC
High Output Drive:
±24
mA at 3 V V
CC
Broad V
CC
Operating Range: 1.65 V to 5.5 V
Power Down High−Impedance Inputs/Outputs
Over−Voltage Tolerance Inputs Facilitate 5 V to 3 V Translation
Proprietary Noise/EMI Reduction Circuitry
CONNECTION DIAGRAMS
IEEE/IEC
SZ74, N9
A
L
YW
KK
XY
Z
UQFN8
1.6X1.6, 0.5P
CASE 523AY
N9KK
XYZ
= Specific Device Code
= Assembly Site
= Wafer Lot Number
= Assembly Start Wee
= 2−Digit Lot Run Traceability Code
= 2−Digit Date Code Format
= Assembly Plant Code
Figure 1. Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
Pin Configurations
Figure 2. USB (Top View)
Figure 3. MicorPakt (Top Through View)
©
Semiconductor Components Industries, LLC, 2019
October, 2020
−
Rev. 4
1
Publication Order Number:
NC7SZ74/D
NC7SZ74
PIN DEFINITIONS
Pin # US8
1
2
3
4
5
6
7
8
Pin # MicroPak
7
6
5
4
3
2
1
8
Name
CK
D
Q
GND
Q
CLR
PR
V
CC
Data Input
Flip−Flop Output
Ground
Flip−Flop Output
Direct Clear Input
Direct Preset Input
Supply Voltage
Description
Clock Pulse Input
FUNCTION TABLE
Inputs
/CLR
L
H
L
H
H
H
/PR
H
L
L
H
H
H
H = HIGH Logic Level
L = LOW Logic Level
D
X
X
X
L
H
X
CK
X
X
X
↑
↑
↓
Qn = No change in data
Z = High Impedance
Q
L
H
H
L
H
Q
n
X = Immaterial
↑
= Rising Edge
Output
/Q
H
L
H
H
L
/Q
n
↓=
Falling Edge
No Change
Function
Clear
Preset
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
or I
GND
T
STG
T
J
T
L
P
D
ESD
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC V
CC
or Ground Current
Storage Temperature Range
Junction Temperature Under Bias
Junction Lead Temperature (Soldering, 10 Seconds)
Power Dissipation in Still Air
Human Body Model, JEDEC:JESD22−A114
Charge Device Model: JEDEC:JESD22−C101
US8
MicroPak−8
V
IN
< 0V
V
OUT
< 0V
Parameter
Min.
−0.5
−0.5
−0.5
−
−
−
−
−65
−
−
−
−
−
−
Max.
6.5
6.5
6.5
−50
−50
±50
±50
+150
+150
+260
500
539
4000
2000
Unit
V
V
V
mA
mA
mA
mA
°C
°C
°C
mW
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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