72245LB15JG datasheet, PDF - EEWORLD Datasheet

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72245LB15JG: DescriptionFIFO, 4KX18, 10ns, Synchronous, CMOS, PQCC68, GREEN, PLASTIC, LCC-68; Categorystorage storage; File Size153KB，16 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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72245LB15JG Overview

FIFO, 4KX18, 10ns, Synchronous, CMOS, PQCC68, GREEN, PLASTIC, LCC-68

72245LB15JG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	LCC
package instruction	QCCJ, LDCC68,1.0SQ
Contacts	68
Reach Compliance Code	compliant
ECCN code	EAR99
Is Samacsys	N
Maximum access time	10 ns
Maximum clock frequency (fCLK)	66.7 MHz
period time	15 ns
JESD-30 code	S-PQCC-J68
JESD-609 code	e3
length	24.2062 mm
memory density	73728 bit
Memory IC Type	OTHER FIFO
memory width	18
Humidity sensitivity level	1
Number of functions	1
Number of terminals	68
word count	4096 words
character code	4000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4KX18
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum standby current	0.005 A
Maximum slew rate	0.06 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	24.2062 mm
Base Number Matches	1

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CMOS SyncFIFO

256 x 18, 512 x 18, 1,024 x 18,

2,048 x 18, and 4,096 x 18

IDT72205LB, IDT72215LB,

IDT72225LB, IDT72235LB,

IDT72245LB

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

FEATURES:

•

256 x 18-bit organization array (IDT72205LB)

512 x 18-bit organization array (IDT72215LB)

1,024 x 18-bit organization array (IDT72225LB)

2,048 x 18-bit organization array (IDT72235LB)

4,096 x 18-bit organization array (IDT72245LB)

10 ns read/write cycle time

Empy and Full flags signal FIFO status

Easy expandable in depth and width

Asynchronous or coincident read and write clocks

Programmable Almost-Empty and Almost-Full flags with

default settings

Half-Full flag capability

Dual-Port zero fall-through time architecture

Output enable puts output data bus in high-impedence state

High-performance submicron CMOS technology

Available in a 64-lead thin quad flatpack (TQFP/STQFP)

and plastic leaded chip carrier (PLCC)

Industrial temperature range (–40°C to +85°C) is available

Green parts available, see ordering information

DESCRIPTION:

write controls. These FIFOs are applicable for a wide variety of data buffering

needs, such as optical disk controllers, Local Area Networks (LANs), and

interprocessor communication.

These FIFOs have 18-bit input and output ports. The input port is controlled

by a free-running clock (WCLK), and an input enable pin (WEN). Data is read

into the synchronous FIFO on every clock when

WEN

is asserted. The output

port is controlled by another clock pin (RCLK) and another enable pin (REN).

The read clock can be tied to the write clock for single clock operation or the

two clocks can run asynchronous of one another for dual-clock operation. An

Output Enable pin (OE) is provided on the read port for three-state control of

the output.

The synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF),

and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The

offset loading of the programmable flags is controlled by a simple state machine,

and is initiated by asserting the Load pin (LD). A Half-Full flag (HF) is available

when the FIFO is used in a single device configuration.

These devices are depth expandable using a Daisy-Chain technique. The

and

pins are used to expand the FIFOs. In depth expansion configu-

ration, First Load (FL) is grounded on the first device and set to HIGH for all

other devices in the Daisy Chain.

The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated

using high-speed submicron CMOS technology.

The IDT72205LB/72215LB/72225LB/72235LB/72245LB are very high

speed, low-power First-In, First-Out (FIFO) memories with clocked read and

FUNCTIONAL BLOCK DIAGRAM

WCLK

D0-D17

INPUT REGISTER

OFFSET REGISTER

WRITE CONTROL

LOGIC

WRITE POINTER

•

RAM ARRAY

256 x 18, 512 x 18

1,024 x 18, 2,048 x 18

4,096 x 18

•

FLAG

LOGIC

READ POINTER

READ CONTROL

LOGIC

)

(

EXPANSION LOGIC

OUTPUT REGISTER

RESET LOGIC

Q0-Q17

RCLK

2766 drw 01

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

NOVEMBER 2017

DSC-2766/4

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