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MT41K256M16TW-107 AIT:P TR

Description
Dynamic Random Access Memory DDR3 4G 256MX16 FBGA
Categorysemiconductor    Memory IC    Dynamic random access memory   
File Size15MB,202 Pages
ManufacturerMicron
Websitehttp://www.micron.com/
Environmental Compliance
Download Datasheet Parametric View All

MT41K256M16TW-107 AIT:P TR Overview

Dynamic Random Access Memory DDR3 4G 256MX16 FBGA

MT41K256M16TW-107 AIT:P TR Parametric

Parameter NameAttribute value
MakerMicron
Product Categorydynamic random access memory
typeSDRAM - DDR3L
Data bus width16 bit
organize256 M x 16
Package/boxFBGA-96
storage4 Gbit
maximum clock frequency933 MHz
Supply voltage - max.1.45 V
Supply voltage - min.1.283 V
Supply current—max.91 mA
Minimum operating temperature- 40 C
Maximum operating temperature+ 95 C
seriesMT41K
EncapsulationCut Tape
EncapsulationMouseReel
EncapsulationReel
Installation styleSMD/SMT
Factory packaging quantity2000
4Gb: x8, x16 Automotive DDR3L SDRAM
Description
Automotive DDR3L SDRAM
MT41K512M8 – 64 Meg x 8 x 8 banks
MT41K256M16 – 32 Meg x 16 x 8 banks
Description
DDR3L SDRAM (1.35V) is a low voltage version of the
DDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM
(Die Rev :E) data sheet specifications when running in
1.5V compatible mode.
Options
• Configuration
– 512 Meg x 8
– 256 Meg x 16
• FBGA package (Pb-free) – x8
– 78-ball (8mm x 10.5mm)
• FBGA package (Pb-free) – x16
– 96-ball (8mm x 14mm)
• Timing – cycle time
– 1.07ns @ CL = 13 (DDR3-1866)
• Product certification
– Automotive
• Operating temperature
– Industrial (–40°C
T
C
+95°C)
– Automotive (–40°C
T
C
+105°C)
– Ultra-high (–40°C
T
C
+125°C)
3
• Revision
Note:
Marking
512M8
256M16
DA
TW
-107
A
IT
AT
UT
:P
Features
• V
DD
= V
DDQ
= 1.35V (1.283–1.45V)
• Backward compatible to V
DD
= V
DDQ
= 1.5V ±0.075V
– Supports DDR3L devices to be backward com-
patible in 1.5V applications
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• T
C
of -40°C to +125°C
– 64ms, 8192-cycle refresh at -40°C to +85°C
– 32ms at +85°C to +105°C
– 16ms at +105°C to +115°C
– 8ms at +115°C to +125°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
• AEC-Q100
• PPAP submission
• 8D response time
Table 1: Key Timing Parameters
Speed Grade
-107
Data Rate (MT/s)
1866
1. Not all options listed can be combined to de-
fine an offered product. Use the part catalog
search on http://www.micron.com for availa-
ble offerings.
2. The datasheet does not support ×4 mode
even though ×4 mode description exists in the
following sections.
3. The UT option use based on automotive us-
age model. Please contact Micron sales repre-
sentative if you have questions.
Target
t
RCD-
t
RP-CL
13-13-13
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.91
13.91
13.91
CCMTD-1725822587-10208
automotive_4gb_ddr3l_v00h.pdf - Rev. F 02/18 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
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