5P35023-109NLGI datasheet, PDF

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5P35023-109NLGI: DescriptionClock generator and supporting products Programmable Clock Generator; Categorysemiconductor The clock and timer IC The clock generator and supporting products; File Size406KB，35 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/; Environmental Compliance

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5P35023-109NLGI Overview

Clock generator and supporting products Programmable Clock Generator

5P35023-109NLGI Parametric

Parameter Name	Attribute value
Maker	IDT (Integrated Device Technology, Inc.)
Product Category	Clock generators and supporting products
series	5P35023
Encapsulation	Tray
Factory packaging quantity	490

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VersaClock

Programmable Clock Generator

5P35023

DATASHEET

Description

The 5P35023 is a VersaClock programmable clock generator

and is designed for low-power, consumer, and

high-performance PCI Express applications. The 5P35023

device is a three PLL architecture design, and each PLL is

individually programmable and allowing for up to six unique

frequency outputs.

The 5P35023 has built-in unique features such as Proactive

Power Saving (PPS), Performance-Power Balancing (PPB),

Overshot Reduction Technology (ORT) and Extreme Low

Power DCO. An internal OTP memory allows the user to store

the configuration in the device. After power up, the user can

change the device register settings through the I

C interface

when I

C mode is selected.

The device has programmable VCO and PLL source selection

to allow the user to do power-performance optimization based

on the application requirements. It also supports three

single-ended outputs and two pair of differential outputs that

support LVCMOS, LVPECL, LVDS and LPHCSL. A Low

Power 32.768kHz clock is supported with only less than 2µA

current consumption for system RTC reference clock.

Features

•

Configurable OE pin function as OE, PD#, PPS or DFC

•

control function

Configurable PLL bandwidth/minimizes jitter peaking

PPS: Proactive Power Saving features save power during

the end device power down mode

PPB: Performance Power Balancing feature allows

minimum power consumption base on required

performance

DFC: Dynamic Frequency Control feature allows user to

dynamically switch between and up to 4 difference

frequencies smoothly

Two PLLs support independent Spread Spectrum clocks to

lower system EMI

Store user configuration into OTP memory

C interface

Key Specifications

•

PCIe clocks phase jitter: PCIe Gen3

•

Differential clocks < 1.5 ps rms jitter integer range 12kHz–

20MHz

Typical Applications

•

PCIe Gen1/2/3 clock generator

•

Consumer application crystal replacements

•

SmartDevice, Handheld, Computing and Consumer

applications

Output Features

•

2 DIFF outputs with configurable LPHSCL, LVDS,

•

LVPECL, LVCMOS output pairs. 1MHz–500MHz (160MHz/

with LVCMOS mode)

3 LVCMOS outputs: 1MHz–160MHz

Maximum 8 LVCMOS outputs as REF + 3 × SE + 2 ×

DIFF_T/C as LVCMOS

Low Power 32.768kHz clock supported for all SE1–SE3

Pin Assignment

VDDDIFF2

VDDSE3

DIFF2B

DIFF2

OE3

SE3

VDDA

SDA_DFCO

SEL_DFC/SCL_DFC1

CLKIN/X2

CLKINB/X1

VBAT

DIFF1

DIFF1B

VDDDIFF1

OE1

SE1

VDDSE1

5P35023

REF

OE2

VDD33

24-pin VFQFPN

5P35023 NOVEMBER 30, 2017

VDDSE2

SE2

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