74LV00PW,112 datasheet, PDF - EEWORLD Datasheet

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74LV00PW,112: DescriptionLogic gate QUAD 2-INPUT NAND; Categorylogic logic; File Size844KB，14 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com

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74LV00PW,112 Overview

Logic gate QUAD 2-INPUT NAND

74LV00PW,112 Parametric

Parameter Name	Attribute value
Brand Name	Nexperia
Maker	Nexperia
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	14
Manufacturer packaging code	SOT402-1
Reach Compliance Code	compliant
Samacsys Description	74LV00 - Quad 2-input NAND gate@en-us
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	5 mm
Logic integrated circuit type	NAND GATE
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
propagation delay (tpd)	31 ns
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm
Base Number Matches	1

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74LV00

Quad 2-input NAND gate

Rev. 4 — 9 December 2015

Product data sheet

1. General description

The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with

74HC00 and 74HCT00.

The 74LV00 provides a quad 2-input NAND function.

2. Features and benefits



Wide operating voltage: 1.0 V to 5.5 V

Optimized for low voltage applications: 1.0 V to 3.6 V

Accepts TTL input levels between V

= 2.7 V and V

= 3.6 V

Typical output ground bounce < 0.8 V at V

= 3.3 V and T

amb

= 25

C

Typical HIGH-level output voltage (V

) undershoot: > 2 V at V

= 3.3 V and

amb

= 25

C



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V



Multiple package options



Specified from

40 C

to +85

C

and from

40 C

to +125

C

3. Ordering information

Table 1.

Ordering information

Package

Temperature range

74LV00D

74LV00DB

74LV00PW

74LV00BQ

40 C

to +125

C

40 C

to +125

C

40 C

to +125

C

40 C

to +125

C

Name

SO14

SSOP14

TSSOP14

Description

plastic small outline package; 14 leads;

body width 3.9 mm

plastic shrink small outline package; 14 leads;

body width 5.3 mm

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

Version

SOT108-1

SOT337-1

SOT402-1

SOT762-1

Type number

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5



0.85 mm

74LV00PW,112 Related Products

	74LV00PW,112	74LV00D,118	74LV00PW,118	74LV00D,112
Description	Logic gate QUAD 2-INPUT NAND	Logic gate QUAD 2-INPUT NAND	Logic gate QUAD 2-INPUT NAND	Logic gate QUAD 2-INPUT NAND
Brand Name	Nexperia	Nexperia	Nexperia	Nexperia
Maker	Nexperia	Nexperia	Nexperia	Nexperia
Parts packaging code	TSSOP	SOIC	TSSOP	SOIC
package instruction	TSSOP,	SOP-14	TSSOP,	SOP-14
Contacts	14	14	14	14
Manufacturer packaging code	SOT402-1	SOT108-1	SOT402-1	SOT108-1
Reach Compliance Code	compliant	compliant	compliant	compliant
series	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e4	e4	e4	e4
length	5 mm	8.65 mm	5 mm	8.65 mm
Logic integrated circuit type	NAND GATE	NAND GATE	NAND GATE	NAND GATE
Humidity sensitivity level	1	1	1	1
Number of functions	4	4	4	4
Number of entries	2	2	2	2
Number of terminals	14	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	SOP	TSSOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	260	NOT SPECIFIED	260
propagation delay (tpd)	31 ns	31 ns	31 ns	31 ns
Maximum seat height	1.1 mm	1.75 mm	1.1 mm	1.75 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	1 V	1 V	1 V	1 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	1.27 mm	0.65 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	30	NOT SPECIFIED	30
width	4.4 mm	3.9 mm	4.4 mm	3.9 mm
Base Number Matches	1	1	1	1

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