GS8160F18/32/36DGT-6.5/7.5
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• Flow Through mode operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• RoHS-compliant 100-lead TQFP package available
1M x 18, 512K x 32, 512K x 36
18Mb Sync Burst SRAMs
6.5 ns – 7.5 ns
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8160F18/32/36DGT operates on a 3.3 V or 2.5 V
power supply. All input are 3.3 V and 2.5 V compatible.
Separate output power (V
DDQ
) pins are used to decouple
output noise from the internal circuits and are 3.3 V and 2.5 V
compatible.
Functional Description
Applications
The GS8160F18/32/36DGT is an 18,874,368-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
Parameter Synopsis
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
-6.5
6.5
6.5
205
225
-7.5
7.5
7.5
190
205
Unit
ns
ns
mA
mA
Flow Through
2-1-1-1
Rev: 1.01 10/2013
1/22
© 2013, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160F18/32/36DGT-6.5/7.5
TQFP Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
BW
B
A
, B
B
B
C
, B
D
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
LBO
V
DD
V
SS
V
DDQ
NC
Type
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pins
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
No Connect
Rev: 1.01 10/2013
5/22
© 2013, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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