= −40°C to +125°C for minimum/maximum specifications, and T
A
= 25°C for
typical specifications, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
THERMAL SHUTDOWN
Threshold
Hysteresis
SYNC INPUT
Input Logic
High
Low
Input Leakage Current
ADAPTIVE MODE INPUT (VSET1)
Input Rising Threshold
Input Hysteresis
PRECISION ENABLING
High Level Threshold
Low Level Threshold
Shutdown Mode
EN1, EN2 Pull-Down Resistance
INPUT CURRENT
Both Channels Enabled
Both Channels Disabled
REFOUT CHARACTERISTICS
Output Voltage
Accuracy
VREG AND VREG_LDO CHARACTERISTICS
Output Voltage
Accuracy
Current Limit
1
POWER-GOOD PIN (PWRGD)
Lower Limit
Lower Hysteresis
Output Voltage Level
Deglitch Time
PVINSYS UNDERVOLTAGE LOCKOUT (UVLO)
Input Voltage
Rising
Falling
1
Symbol
V
PVIN1
, V
PVINSYS
V
PVIN2
T
SD
T
SD-HYS
Min
4.2
0.65
Typ Max Unit Test Conditions/Comments
15
V
5
V
155
15
°C
°C
T
J
rising
V
IH
V
IL
V
I-LEAKAGE
V
ADPR
V
ADPH
V
TH_H
V
TH_L
V
TH_S
R
ENPD
I
STBY-NOSW
I
SHUTDOWN
V
REFOUT
1.1
0.4
1
2.5
16
1.125 1.15 1.175
1.025 1.05 1.075
0.4
1.5
0.5
5
2.0
−0.5
1
10
V
V
µA
V
mV
V
V
V
MΩ
mA
µA
No load
T
J
= −40°C to +125°C
V
+0.5 %
V
%
mA
%
%
mV
µs
Nominal VOUT1 and nominal VFB2P/VFB2N low threshold
Nominal VOUT1 and nominal VFB2P/VFB2N low hysteresis
Sink current (I
SINK
) = 1 mA
V
REG
, V
REG_LDO
−2
10
PWRGD
F
PWRGD
FH
V
OL
t
PWRGDD
80
5
+2
85
2.5
25
60
90
50
UVLO
PVINSYSRISE
UVLO
PVINSYSFALL
3.9
4.2
V
V
Do not use VREG and VREG_LDO to supply the external loads. This current limit protects against a pin short to ground.
Rev. 0 | Page 3 of 29
ADP5003
BUCK REGULATOR SPECIFICATIONS
Data Sheet
V
PVIN1
= V
PVINSYS
= 4.2 V to 15 V, V
PVIN2
= 0.65 V to 5 V, T
J
= −40°C to +125°C for minimum/maximum specifications, and T
A
= 25°C for typical
specifications, unless otherwise noted.
Table 2.
Parameter
OUTPUT CHARACTERISTICS
Programmable Output Voltage Range
1
Buck Regulator Gain
Error Amplifier Transconductance
Buck Output Voltage Accuracy
2
Regulation
Line
Load
Total Output Voltage Accuracy
OPERATING SUPPLY CURRENT
SW1 CHARACTERISTICS
SW1 On Resistance
Current Limit 1
Symbol
V
VOUT1
A
BUCK
g
m1
σ
VOUT1
(ΔV
VOUT1
/V
VOUT1
)/ΔV
PVIN1
(ΔV
VOUT1
/V
VOUT1
)/ΔI
VOUT1
σ
BUCK
I
IN
R
PFET
R
NFET
I
LIMIT1
Min
0.6
509
−1
2.5
600
Typ
Max
5.0
661
+1
Unit
V
µS
%
%/V
%/A
%
mA
200
100
mΩ
mΩ
A
A
V/ns
ns
ns
Ω
ms
ms
nA
MHz
MHz
MHz
ns
ns
Test Conditions/Comments
Load 1 current (I
LOAD1
) = 10 mA
I
LOAD1
= 10 mA
0 mA ≤ I
LOAD1
≤ 3 A, V
PVIN1
= 12 V
4.2 V ≤ V
PVIN1
≤ 15 V, 1 mA ≤ I
LOAD1
≤ 3 A
I
LOAD1
= 0 mA, LDO disabled
V
PVIN1
= 15 V (PVIN1 to SW1)
V
PVIN1
= 15 V (SW1 to PGND1)
Negative channel field effect
transistor (NFET) switch valley
current limit
Negative current limit
V
PVIN1
= 15 V, I
VOUT1
= 1 A
0.004
0.04
±1.5
3.8
130
60
3.5
−1
Slew Rate
Minimum On Time
3
Minimum Off Time
BUCK REGULATOR ACTIVE PULL DOWN
BUCK REGULATOR SOFT START (SS)
HICCUP TIME
VSETx ADJUSTABLE INPUT BIAS CURRENT
OSCILLATOR
Internal Switching Frequency 1
Internal Switching Frequency 2
SYNC
Frequency Range
Minimum Pulse Width
Positive
Negative
1
2
SLEW
SW1
t
MIN_ON
t
MIN_OFF
R
PDWN-B
t
SSBUCK
t
HICCUP
I
VSET1
, I
VSET2
f
SW1
f
SW2
f
SYNC
2.25
0.26
0.3
20
10
1.6
35
100
90
2
33
10
2.5
0.3
128
Channel disabled
150
2.75
0.34
2.5
4.2 V ≤ V
PVINSYS
≤ 15 V
RT current (I
RT
) = 10 µA
I
RT
= 1 µA
The switching frequency, minimum on time, and minimum off time dictates the output voltage range.
The buck output voltage accuracy is relative to the nominal output voltage and accounts for reference voltage, gain, and offset error.
3
The minimum on time indicates the minimum turn on time to ensure fixed frequency switching.
Rev. 0 | Page 4 of 29
Data Sheet
LDO SPECIFICATIONS
V
PVIN1
= V
PVINSYS
= 4.2 V to 15 V, V
PVIN2
= 0.65 V to 5 V, LDO headroom voltage (V
HR
) = 300 mV, T
J
= −40°C to +125°C for
minimum/maximum specifications, and T
A
= 25°C for typical specifications, unless otherwise noted.
Table 3.
Parameter
OUTPUT CHARACTERISTICS
Programmable Output Voltage Range
1
LDO Gain
Output Voltage Accuracy
2
Regulation
Line
Load
Total Output Voltage Accuracy
OPERATING SUPPLY CURRENT
MINIMUM VOLTAGE REQUIREMENTS
PVINSYS to PVOUT2
3
VREG_LDO to PVOUT2
4
Dropout
5
CURRENT-LIMIT THRESHOLD
6
LDO SOFT START (SS) TIME
LDO ACTIVE PULL-DOWN
OUTPUT NOISE
LDO POWER SUPPLY REJECTION RATIO
V
PVOUT2
= 1.3 V
Symbol
V
PVOUT2
A
LDO
σ
PVOUT2
(ΔV
PVOUT2
/V
PVOUT2
)/ΔV
PVIN2
(ΔV
PVOUT2
/V
PVOUT2
)/ΔI
PVOUT2
σ
LDO
I
GND
Min
0.6
1.65
−1
0.007
0.08
±1.5
1.8
2.3
1.5
1.35
100
3.1
400
300
3
87
82
61
38
89
83
61
37
4.5
2.5
+1
%
%/V
%/A
%
mA
mA
V
V
mV
A
µs
Ω
µV rms
dB
dB
dB
dB
dB
dB
dB
dB
Typ
Max
3.3
Unit
V
ADP5003
Test Conditions/Comments
Load 2 current (I
LOAD2
) = 150 mA
(V
PVOUT2
+ V
HR
) ≤ V
PVIN2
≤ 6 V,
I
LOAD2
= 100 mA
10 mA ≤ I
LOAD2
≤ 3 A
(V
PVOUT2
+ V
HR
) ≤ V
PVIN2
≤ 6 V,
10 mA ≤ I
LOAD2
≤ 3 A
I
LOAD2
= 0 μA
I
LOAD2
= 3 A
I
LOAD2
= 3 A
Required to drive NFET
V
LDO-PVINSYS
V
LDO-VREG_LDO
V
DROPOUT
I
LIMIT2
t
SSLDO
R
PDWNLDO
N
PVOUT2
PSRR
LDO
V
PVOUT2
= 3.3 V
Channel disabled
10 Hz to 100 kHz, I
OUT
= 1 A
V
PVIN2
= V
PVOUT2
+ 0.3 V, I
OUT
= 1 A
1 kHz
10 kHz
100 kHz
1000 kHz
1 kHz
10 kHz
100 kHz
1000 kHz
Limited by minimum PVINSYS to PVOUT2 and VREG_LDO to PVOUT2 voltage.
The LDO output voltage accuracy is relative to the nominal output voltage and accounts for reference voltage, gain, and offset error.
3
PVINSYS must be higher than PVOUT2 for V
LDO-PVINSYS
to keep the LDO regulating.
4
PVOUT2 must be lower than VREG_LDO for V
LDO-VREG_LDO
to keep the LDO regulating.
5
The dropout voltage is the input to output voltage differential when the input voltage is set to the nominal output voltage.
6
The current-limit threshold is the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output
voltage is the current that causes the output voltage to drop to 90% of 1.0 V or 0.9 V.
1
2
ADAPTIVE HEADROOM CONTROLLER SPECIFICATIONS
V
PVIN1
= V
PVINSYS
= 4.2 V to 15 V, V
PVIN2
= 0.65 V to 5 V, T
J
= −40°C to +125°C for minimum/maximum specifications, and T
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