Features
•
Complies with Intel
®
Low-Pin Count (LPC) Interface Specification Revision 1.1
•
•
– Supports both Firmware Hub (FWH) and LPC Memory Read and Write Cycles
Auto-detection of FWH and LPC Memory Cycles
– Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets
– Can Be Used as LPC Flash for Non-Intel Chipsets
Flexible, Optimized Sectoring for BIOS Applications
– 16-Kbyte Top Boot Sector, Two 8-Kbyte Sectors, One 32-Kbyte Sector,
Three 64-Kbyte Sectors
– Or Memory Array Can Be Divided Into Four Uniform 64-Kbyte Sectors for Erasing
Two Configurable Interfaces
– FWH/LPC Interface for In-System Operation
– Address/Address Multiplexed (A/A Mux) Interface for Programming during
Manufacturing
FWH/LPC Interface
– Operates with the 33 MHz PCI Bus Clock
– 5-signal Communication Interface Supporting Byte Reads and Writes
– Two Hardware Write Protect Pins: TBL for Top Boot Sector and WP for All
Other Sectors
– Five General-purpose Input (GPI) Pins for System Design Flexibility
– Identification (ID) Pins for Multiple Device Selection
– Sector Locking Registers for Individual Sector Read and Write Protection
A/A Mux Interface
– 11-pin Multiplexed Address and 8-pin Data Interface
– Facilitates Fast In-System or Out-of-System Programming
Single Voltage Operation
– 3.0V to 3.6V Supply Voltage for Read and Write Operations
Industry-Standard Package Options
– 32-lead PLCC
– 40-lead TSOP
•
•
2-megabit
Firmware Hub
and Low-Pin
Count Flash
Memory
AT49LH002
Not Recommended
for New Design
Contact
Atmel to discuss
the latest design in trends
and options
•
•
•
Description
The AT49LH002 is a Flash memory device designed for use in PC and notebook BIOS
applications. The device complies with version 1.1 of Intel’s LPC Interface Specifica-
tion, providing support for both FWH and LPC memory read and write cycles. The
device can also automatically detect the memory cycle type to allow the AT49LH002
to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets.
Pin Configurations
PLCC
GPI2 [A8]
GPI3 [A9]
RST [RST]
NC
VCC
CLK [R/C]
GPI4 [A10]
NC
[IC] IC
NC
NC
NC
NC
[A10] GPI4
NC
[R/C] CLK
VCC
NC
[RST] RST
NC
NC
[A9] GPI3
[A8] GPI2
[A7] GPI1
[A6] GPI0
[A5] WP
[A4] TBL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TSOP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
VCC
FWH4/LFRAME [WE]
INIT [OE]
RES [RDY/BSY]
RES [I/O7]
RES [I/O6]
RES [I/O5]
RES [I/O4]
VCC
GND
GND
FWH3/LAD3 [I/O3]
FWH2/LAD2 [I/O2]
FWH1/LAD1 [I/O1]
FWH0/LAD0 [I/O0]
ID0 [A0]
ID1 [A1]
ID2 [A2]
ID3 [A3]
[I/O1] FWH1/LAD1
[I/O2] FWH2/LAD2
GND
[I/O3] FWH3/LAD3
[I/O4] RES
[I/O5] RES
[I/O6] RES
14
15
16
17
18
19
20
[A7] GPI1
[A6] GPI0
[A5] WP
[A4] TBL
[A3] ID3
[A2] ID2
[A1] ID1
[A0] ID0
[I/O0] FWH0/LAD0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
IC [IC]
GND
NC
NC
VCC
INIT [OE]
FWH4/LFRAME [WE]
RES [RDY/BSY]
RES [I/O7]
Note:
[ ] Designates A/A Mux Interface.
3377B–FLASH–9/03
1
The sectoring of the AT49LH002’s memory array has been optimized to meet the needs of
today’s BIOS applications. By optimizing the size of the sectors, the BIOS code memory space
can be used more efficiently. Because certain BIOS code modules must reside in their own
sectors by themselves, the wasted and unused memory space that occurred with previous
generation BIOS Flash memory devices can be greatly reduced. This increased memory
space efficiency allows additional BIOS routines to be developed and added while still main-
taining the same overall device density.
The memory array of the AT49LH002 can be sectored in two ways simply by using two differ-
ent erase commands. Using one erase command allows the device to contain a total of seven
sectors comprised of a 16-Kbyte boot sector, two 8-Kbyte sectors, a 32-Kbyte sector, and
three 64-Kbyte sectors. The 16-Kbyte boot sector is located at the top (uppermost) of the
device’s memory address space and can be hardware write protected by using the TBL pin.
Alternatively, by using a different erase command, the memory array can be arranged into four
even erase sectors of 64-Kbyte each, allowing the top 64-Kbyte region to be used as the boot
sector. The TBL pin, when used with the second erase command, will hardware write protect
the entire top 64-Kbyte region against erasure.
The AT49LH002 supports two hardware interfaces: The FWH/LPC interface for In-System
operations and the A/A Mux interface for programming during manufacturing. The Interface
Configuration (IC) pin of the device provides the control between these two interfaces. An
internal Command User Interface (CUI) serves as the control center between the device inter-
faces and the internal operation of the nonvolatile memory. A valid command sequence
written to the CUI initiates device automation.
Specifically designed for use in 3-volt systems, the AT49LH002 supports read, program, and
erase operations with a supply voltage range of 3.0V to 3.6V. No separate voltage is required
for programming and erasing.
The AT49LH002 utilizes fixed program and erase times, independent of the number of pro-
gram and erase cycles that have occurred. Therefore, the system does not need to be
calibrated or correlated to the cumulative number of program and erase cycles.
Block Diagram
TBL
WP
INIT
CLK
FWH4/LFRAME
FWH/LAD[3:0]
ID[3:0]
GPI[4:0]
IC
RST
R/C
A[10:0]
I/O[7:0]
OE
WE
RDY/BSY
FWH/LPC
INTERFACE
CONTROL LOGIC
I/O BUFFERS
AND LATCHES
ADDRESS LATCH
INTERFACE CONTROL
AND LOGIC
Y-DECODER
Y-GATING
A/A MUX
INTERFACE
X-DECODER
FLASH
MEMORY
ARRAY
2
AT49LH002
3377B–FLASH–9/03
AT49LH002
Device Memory Map
Sector
6
5
4
3
2
1
0
Type
Sub-sector
Sub-sector
Sub-sector
Sub-sector
Main Sector
Main Sector
Main Sector
Size (Bytes)
16K
8K
8K
32K
64K
64K
64K
Address Range
03C000H - 03FFFFH
03A000H - 03BFFFH
038000H - 039FFFH
030000H - 037FFFH
020000H - 02FFFFH
010000H - 01FFFFH
000000H - 00FFFFH
Pin Description
Table 1 provides a description of each of the device pins. Most of the pins have dual functionality in that they are used for
both the FWH/LPC interface as well as the A/A Mux interface.
Table 1.
Signal Descriptions
Interface
Symbol
IC
Name and Function
INTERFACE COMMUNICATION:
The IC pin determines which interface is
operational. If the IC pin is held high, then the A/A Mux interface is enabled, and if
the IC pin is held low, then the FWH/LPC interface is enabled. The IC pin must be
set at power-up or before returning from a reset condition and cannot be changed
during device operation.
The IC pin is internally pulled-down with a resistor valued between 20 kΩ and
100 kΩ, so connection of this pin is not necessary if the FWH/LPC interface will
always be used in the system. If the IC pin is driven high to enable the A/A Mux
interface, then the pin will exhibit some leakage current.
FWH/LPC CLOCK:
This pin is used to provide a clock to the device. This pin is
usually connected to the 33 MHz PCI clock and adheres to the PCI specification.
This pin is used as the R/C pin in the A/A Mux interface.
FWH INPUT/LPC FRAME:
This pin is used to indicate the start of a FWH or LPC
data transfer operation. The pin is also used to abort a FWH or LPC cycle in
progress.
This pin is used as the WE pin in the A/A Mux interface.
FWH/LPC ADDRESS AND DATA:
These pins are used for FWH/LPC bus
information such as addresses, data, and command inputs/outputs.
These pins are used as the I/O[3:0] pins in the A/A Mux interface.
INTERFACE RESET:
The RST pin is used for both FWH/LPC and A/A Mux
interfaces. When the RST pin is driven low, write operations are inhibited, internal
automation is reset, and the FWH/LAD[3:0] pins (when using the FWH/LPC
interface) are put into a high-impedance state. When the device exits the reset
state, it will default to the read array mode.
FWH/LPC
X
A/A Mux
X
Type
Input
CLK
X
Input
FWH4/
LFRAME
X
Input
FWH/
LAD[3:0]
RST
X
Input/
Output
X
Input
X
3
3377B–FLASH–9/03
Table 1.
Signal Descriptions (Continued)
Interface
Symbol
INIT
Name and Function
PROCESSOR RESET/INITIALIZE:
The INIT pin is used as a second reset pin for
In-System operation and functions identically to the RST pin. The INIT pin is
designed to be connected to the chipset’s INIT signal.
The maximum voltage to be applied to the INIT pin depends on the processor’s or
chipset’s specifications. Systems must take care to not violate processor or chipset
specifications regarding the INIT pin voltage.
This pin is used as the OE pin in the A/A Mux interface.
TOP BOOT SECTOR LOCK:
When the TBL pin is held low, program and erase
operations cannot be performed to the 16-Kbyte top boot sector regardless of the
state of the Sector Locking Registers. In addition, the TBL pin will either protect the
16-Kbyte top boot sector or the uppermost 64-Kbyte region against erasures
depending on which sector erase command has been issued to the device. Please
refer to the Sector Protection section for more details.
If the TBL pin is held high, then hardware write protection for the top boot sector will
be disabled. However, register-based sector protection will still apply. The state of
the TBL pin does not affect the state of the Sector Locking Registers.
This pin is used as the A4 pin in the A/A Mux interface.
WRITE PROTECT:
The WP pin is used to protect all remaining sectors that are not
being used for the top boot region. See the “Sector Protection” section on page 16
for more details.
If the WP pin is high, then hardware write protection for all of the sectors except the
top boot sector will be disabled. Register-based sector protection, however, will still
apply. The state of the WP pin does not affect the state of the Sector Locking
Registers.
This pin is used as the A5 pin in the A/A Mux interface.
IDENTIFICATION INPUTS:
These four pins are part of the mechanism that allows
multiple devices to be attached to the same bus. The strapping of these pins is
used to assign an ID to each device. The boot device must have ID[3:0] = 0000,
and it is recommended that all subsequent devices should use sequential up-count
strapping (e.g., 0001, 0010, 0011, etc.).
Values presented on the ID[3:0] pins are only recognized when the device is
operated as a FWH device. If the device is operating as an LPC Flash, then the
ID[3:0] pins are ignored.
The ID[3:0] pins are internally pulled-down with resistors valued between 20 kΩ and
100 kΩ when using the FWH/LPC interface, so connection of these pins is not
necessary if only a single device will be used in a system. Any pins intended to be
low may be left floating. Any ID pin driven high will exhibit some leakage current.
These pins are used as the A[3:0] pins in the A/A Mux interface.
GENERAL-PURPOSE INPUTS:
The individual GPI pins can be used for additional
board flexibility. The state of the GPI pins can be read, using the FWH/LPC
interface, through the GPI register. The GPI pins should be at their desired state
before the start of the PCI clock cycle during which the read is attempted, and they
should remain at the same level until the end of the read cycle.
The voltages applied to the GPI pins must comply with the devices V
IH
and V
IL
requirements. Any unused GPI pins must not be left floating.
These pins are used as the A[10:6] pins in the A/A Mux interface.
ADDRESS INPUTS:
These pins are used for inputting the multiplexed address
values when using the A/A Mux interface. The addresses are latched by the rising
and falling edge of R/C pin.
FWH/LPC
X
A/A Mux
Type
Input
TBL
X
Input
WP
X
Input
ID[3:0]
FWH
Input
GPI[4:0]
X
Input
A[10:0]
X
Input
4
AT49LH002
3377B–FLASH–9/03
AT49LH002
Table 1.
Signal Descriptions (Continued)
Interface
Symbol
I/O[7:0]
Name and Function
DATA INPUTS/OUTPUTS:
The I/O pins are used in the A/A Mux interface to input
data and commands during write cycles and to output data during memory array,
Status Register, and identifier code read cycles. Data is internally latched during a
write cycle.
The I/O pins will be in a high-impedance state when the outputs are disabled.
ROW/COLUMN ADDRESS SELECT:
In the A/A Mux interface, the R/C pin is used
to latch the address values presented on the A[10:0] pins. The row addresses
(A10 - 0) are latched on the falling edge of R/C, and the column addresses
(A17 - A11) are latched on the rising edge of R/C.
OUTPUT ENABLE:
The OE pin is used in the A/A Mux interface to control the
device’s output buffers during a read cycle.
The I/O[7:0] pins will be in high-impedance state when the OE pin is deasserted
(high).
WRITE ENABLE:
The WE pin is used in the A/A Mux interface to control write
operations to the device.
READY/BUSY:
The RDY/BSY pin provides the device’s ready/busy status when
using the A/A Mux interface. The RDY/BSY pin is a reflection of Status Register
bit 7, which is used to indicate whether a program or erase operation has been
completed.
Use of the RDY/BSY pin is optional, and the pin does not need to be connected.
DEVICE POWER SUPPLY:
The VCC pin is used to supply the source voltage to
the device. Program and erase operations are inhibited when V
CC
is less than or
equal to V
LKO
.
Operations at invalid V
CC
voltages may produce spurious results and should not be
attempted.
GROUND:
The ground reference for the power supply. GND should be connected
to the system ground.
NO CONNECT:
NC pins have no internal connections and can be driven or left
floating. If the pins are driven, the voltage levels should comply with V
IH
and V
IL
requirements.
RESERVED:
RES pins are reserved for future device enhancements or
functionality. These pins may be left floating or may be driven. If the pins are driven,
the voltage levels should comply with V
IH
and V
IL
requirements.
These pins are used as the RDY/BSY and I/O[7:4] pins in the A/A Mux interface.
X
FWH/LPC
A/A Mux
X
Type
Input/
Output
R/C
X
Input
OE
X
Input
WE
RDY/BSY
X
X
Input
Output
VCC
X
Power
GND
NC
X
X
X
X
Power
–
RES
X
X
–
5
3377B–FLASH–9/03
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