I am a FPGA newbie, and now I have a Verilog question I would like to ask
For example, there is an input data
input [16:0] REG
For ease of use, I now want to disassemble REG, such as
a = REG[16:8];
b ...
This is the source code of the original author of tsg9456 in actual application, I hope it can help everyoneRun codeCopy code#include "synth.h"//-------------------------------------------------------...
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