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WS57C51C-70D

Description
HIGH SPEED 16K x 8 CMOS PROM/RPROM
Categorystorage    storage   
File Size39KB,7 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Download Datasheet Parametric View All

WS57C51C-70D Overview

HIGH SPEED 16K x 8 CMOS PROM/RPROM

WS57C51C-70D Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSTMicroelectronics
Parts packaging codeDIP
package instruction0.600 INCH, CERDIP-28
Contacts28
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time70 ns
JESD-30 codeR-GDIP-T28
JESD-609 codee0
length37.215 mm
memory density131072 bit
Memory IC TypeUVPROM
memory width8
Number of functions1
Number of terminals28
word count16384 words
character code16000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16KX8
Output characteristics3-STATE
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeWDIP
Encapsulate equivalent codeDIP28,.6
Package shapeRECTANGULAR
Package formIN-LINE, WINDOW
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height5.72 mm
Maximum slew rate0.107 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width15.24 mm
Base Number Matches1
WS57C51C
HIGH SPEED 16K
x
8 CMOS PROM/RPROM
KEY FEATURES
Very Fast Access Time
35 ns
Pin Compatible with Am27S51
and N82HS1281
Immune to Latch-Up
Up to 200 mA
Low Power Consumption
Fast Programming
ESD Protection Exceeds 2000 V
GENERAL DESCRIPTION
The WS57C51C is a High Performance 128K UV Erasable Electrically Re-Programmable Read Only Memory
(RPROM). It is manufactured in an advanced CMOS technology which enables it to operate at Bipolar PROM
speeds while consuming only 25% of the power required by its Bipolar counterparts.
A further advantage of the WS57C51C over Bipolar PROM devices is the fact that it utilizes a proven EPROM
technology. This enables the entire memory array to be tested for switching characteristics and functionality after
assembly. Unlike devices which cannot be erased, every WS5751C in a windowed package is 100% tested with
worst case test patterns both before and after assembly.
The WS57C51C provides a low power alternative to those designs which are committed to a Bipolar PROM
footprint. It is a direct drop-in replacement for a Bipolar PROM of the same architecture (16K x 8). No software,
hardware or layout changes need be performed.
BLOCK DIAGRAM
EPROM ARRAY
PIN CONFIGURATION
TOP VIEW
Chip Carrier
A
6
A
7
A
8
A
9
V
CC
A
10
A
11
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
8
A6 - A13
ROW
ADDRESSES
ROW
DECODER
CERDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A10
A11
A12
A13
CS1/VPP
CS2
CS3
CS4
O
7
O
6
O
5
O
4
O
3
131,072 BITS
6
A0 - A5
COLUMN
ADDRESSES
COLUMN
DECODER
SENSE
AMPLIFIERS
CS1/ V
PP
CS2
CS3
CS4
8
A
5
A
4
A
3
A
2
A
1
A
0
NC
O
0
O
1
4 3 2
32 31 30
1
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
O
2
NC
GND
A
12
A
13
CS1/V
PP
CS2
CS3
CS4
NC
O
7
O
6
O
3
NC O
4
O
5
OUTPUTS
PRODUCT SELECTION GUIDE
PARAMETER
Address Access Time (Max)
CS to Output Valid Time (Max)
57C51C-35
35 ns
20 ns
57C51C-45
45 ns
20 ns
57C51C-55
55 ns
25 ns
57C51C-70
70 ns
30 ns
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