PCA9535E, PCA9535EC
16-bit Low-Power I/O
Expander for I
2
C Bus with
Interrupt
The PCA9535E and PCA9535EC devices provide 16 bits of
General Purpose parallel Input / Output (GPIO) expansion through the
I
2
C−bus / SMBus.
The PCA9535E and PCA9535EC consist of two 8−bit
Configuration (Input or Output selection); Input, Output and Polarity
Inversion (active−HIGH or active−LOW operation) registers. At
power on, all I/Os default to inputs. Each I/O may be configured as
either input or output by writing to its corresponding I/O configuration
bit. The data for each Input or Output is kept in its corresponding Input
or Output register. The Polarity Inversion register may be used to
invert the polarity if the read register. All registers can be read by the
system master.
The PCA9535E, identical to the PCA9655E but with the internal
I/O pull−up resistors removed, has greatly reduced power
consumption when the I/Os are held LOW.
The PCA9535EC is identical to the PCA9535E but with
high−impedance open−drain outputs at all the I/O pins.
The PCA9535E and PCA9535EC provide an open−drain interrupt
output which is activated when any input state differs from its
corresponding input port register state. The interrupt output is used to
indicate to the system master that an input state has changed. The
power−on reset sets the registers to their default values and initializes
the device state machine.
Three hardware pins (AD0, AD1, AD2) are used to configure the
2
C−bus slave address of the device. The I
2
C−bus slave addresses of
I
the PCA9535E and PCA9535EC are the same as the PCA9655E. This
allows up to 64 of these devices in any combination to share the same
I
2
C−bus/SMBus.
Features
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MARKING
DIAGRAMS
SOIC−24
DW SUFFIX
CASE 751E
PCA9535E(C)
AWLYYWWG
TSSOP−24
DT SUFFIX
CASE 948H
PCA95
35E(C)G
ALYW
1
WQFN24
MT SUFFIX
CASE 485BG
PCA
9535E(C)
ALYWG
G
•
•
•
•
•
•
•
•
•
•
V
DD
Operating Range: 1.65 V to 5.5 V
SDA Sink Capability: 30 mA
5.5 V Tolerant I/Os
Polarity Inversion Register
Active LOW Interrupt Output
Low Standby Current
Noise Filter on SCL/SDA Inputs
No Glitch on Power−up
Internal Power−on Reset
64 Programmable Slave Addresses using Three
Address Pins
•
16 I/O Pins which Default to 16 Inputs
•
I
2
C SCL Clock Frequencies Supported:
Standard Mode: 100 kHz
Fast Mode: 400 kHz
Fast Mode +: 1 MHz
XXXX = Specific Device Code
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
•
ESD Performance: 3000 V Human Body Model, 400 V
Machine Model
•
NLV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change
Requirements; AEC−Q100 Qualified and PPAP
Capable
•
These are Pb−Free Devices
©
Semiconductor Components Industries, LLC, 2015
1
March, 2017 − Rev. 7
Publication Order Number:
PCA9535E/D
PCA9535E, PCA9535EC
Table 2. MAXIMUM RATINGS
Symbol
V
DD
V
I/O
I
I
I
O
I
DD
I
GND
P
TOT
P
OUT
T
STG
T
L
T
J
q
JA
DC Supply Voltage
Input / Output Pin Voltage
Input Current
Output Current
DC Supply Current
DC Ground Current
Total Power Dissipation
Power Dissipation per Output
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 1)
SOIC−24
TSSOP−24
WQFN24
Parameter
Value
−0.5 to +7.0
−0.5 to +7.0
$20
$50
$100
$600
600
200
−65 to +150
260
150
85
91
68
Level 1
UL 94 V−0 @
0.125 in
> 3000
> 400
N/A
$100
V
Unit
V
V
mA
mA
mA
mA
mW
mW
°C
°C
°C
°C/W
MSL
F
R
V
ESD
Moisture Sensitivity
Flammability Rating Oxygen Index: 28 to 34
ESD Withstand Voltage Human Body Mode (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Latchup Performance Above V
DD
and Below GND at 125°C (Note 5)
I
LATCHUP
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functional-
ity should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
2. Tested to EIA / JESD22−A114−A.
3. Tested to EIA / JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA / JESD78.
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol
V
DD
V
I/O
T
A
Positive DC Supply Voltage
Switch Input / Output Voltage
Operating Free−Air Temperature
Parameter
Min
1.65
0
−55
Max
5.5
5.5
+125
Unit
V
V
°C
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4
PCA9535E, PCA9535EC
Table 4. DC ELECTRICAL CHARACTERISTICS
V
DD
= 1.65 V to 5.5 V, unless otherwise specified.
T
A
= −555C to +1255C
Symbol
SUPPLIES
I
STB
Standby Current (Note 6)
Standby mode; no load;
V
I
= 0 V; f
SCL
= 0 Hz; I/O = inputs
V
I
= V
DD
; f
SCL
= 0 Hz; I/O = inputs
mA
39
39
1.5
100
100
1.65
V
Parameter
Conditions
Min
Typ
Max
Unit
V
POR
Power−On Reset Voltage (Note 7)
INPUT SCL; INPUT / OUTPUT SDA
V
IH
V
IL
I
OL
I
L
C
I
I/Os
V
IH
V
IL
I
OL
High−Level Input Voltage
Low−Level Input Voltage
Low−Level Output Current
(Note 8)
V
OL
= 0.5 V; V
DD
= 1.65 V
V
OL
= 0.5 V; V
DD
= 2.3 V
V
OL
= 0.5 V; V
DD
= 3.0 V
V
OL
= 0.5 V; V
DD
= 4.5 V
I
OL(tot)
V
OH
Total Low−Level Output Current
(Note 8)
High−Level Output Voltage
(PCA9535E Only)
V
OL
= 0.5 V; V
DD
= 4.5 V
I
OH
= −3 mA; V
DD
= 1.65 V
I
OH
= −4 mA; V
DD
= 1.65 V
I
OH
= −8 mA; V
DD
= 2.3 V
I
OH
= −10 mA; V
DD
= 2.3 V
I
OH
= −8 mA; V
DD
= 3.0 V
I
OH
= −10 mA; V
DD
= 3.0 V
I
OH
= −8 mA; V
DD
= 4.5 V
I
OH
= −10 mA; V
DD
= 4.5 V
I
L
C
I/O
Input Leakage Current
Input / Output Capacitance
(Note 9)
V
DD
= 5.5 V; V
I
= V
DD
or 0 V
3.7
1.2
1.1
1.8
1.7
2.6
2.5
4.1
4.0
$1
5
mA
pF
8
12
17
25
20
28
35
42
400
mA
V
0.7 x V
DD
0.3 x V
DD
V
V
mA
High−Level Input Voltage
Low−Level Input Voltage
Low−Level Output Current
Leakage Current
Input Capacitance
V
OL
= 0.4 V; V
DD
< 2.3 V
V
OL
= 0.4 V; V
DD
w
2.3 V
V
I
= V
DD
or 0 V
V
I
= 0 V
4.6
10
20
$1
6
0.7 x V
DD
0.3 x V
DD
V
V
mA
mA
pF
INTERRUPT (INT)
I
OL
C
O
Low−Level Output Current
Output Capacitance
V
OL
= 0.4 V
6
2.1
5
mA
pF
INPUTS AD0, AD1, AD2
V
IH
V
IL
I
L
C
I
High−Level Input Voltage
Low−Level Input Voltage
Leakage Current
Input Capacitance
V
I
= V
DD
or 0 V
2.4
0.7 x V
DD
0.3 x V
DD
$1
5
V
V
mA
pF
6. The device is in standby mode after an I2C stop command.
7. The power−on reset circuit resets the I
2
C bus logic with V
DD
< V
POR
and set all I/Os to logic 1 upon power−up. Thereafter, V
DD
must
be lower than 0.2 V to reset the part.
8. Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits.
9. The value is not tested, but verified on sampling basis.
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