SVF532R2K2CMK4R datasheet, PDF

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SVF532R2K2CMK4R: DescriptionCORTEX- M4 PRIMARY CORE CORTEX; Categorysemiconductor The embedded processor and controller; File Size2MB，125 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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SVF532R2K2CMK4R Overview

CORTEX- M4 PRIMARY CORE CORTEX

SVF532R2K2CMK4R Parametric

Parameter Name	Attribute value
core processor	ARM® Cortex®-A5 + Cortex®-M4
Number of cores/bus width	2 코어, 32 bits
speed	400MHz，133MHz
Coprocessor/DSP	Multimedia; NEON™ MPE
RAM controller	LPDDR2，DDR3，DRAM
graphics acceleration	yes
display and interface controller	DCU，GPU，LCD，VideoADC，VIU
Ethernet	10/100 Mbps（2）
SATA	-
USB	USB 2.0 OTG + PHY（1）
Voltage - I/O	3.3V
Operating temperature	-40°C ~ 85°C（TA）
security features	ARM TZ, Hash, RNG, RTC, RTIC, Secure JTAG, SNVS, TZ ASC, TZ WDOG
Package/casing	364-LFBGA
Supplier device packaging	364-LFBGA（17x17）
Additional interface	CAN，I²C，IrDA，LIN，MediaLB，SCI，SDHC，SPI，UART/USART

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NXP Semiconductors

Data Sheet: Technical Data

Document Number VYBRIDRSERIESEC

Rev. 8, 01/2018

VF3xxR, VF5xxR

Features

• Operating characteristics

– Voltage range 3 V to 3.6 V

– Temperature range(ambient) -40 °C to 85 °C

• ARM® Cortex® A5 Core features

– Up to 400 MHz ARM® Cortex® A5 core

– 32 KB/32 KB I/D L1 Cache

– 1.6 DMIPS/MHz based on ARMv7 architecture

– NEON™ MPE (Media Processing Engine) Co-

processor

– Double Precision Floating Point Unit

– 512 KB L2 cache (on selected part numbers only)

• ARM Cortex M4 Core features

– Up to 133 MHz ARM Cortex M4

– Integrated DSP capability

– 64 KB Tightly Coupled Memory (TCM)

– 16 KB/16 KB I/D L1 Cache

– 1.25 DMIPS/MHz based on ARMv7 architecture

• Clocks

– 24 MHz crystal oscillator

– 32 kHz crystal oscillator

– Internal reference clocks (128 KHz and 24 MHz)

– Phase Locked Loops (PLLs)

– Low Jitter Digital PLLs

• System debug, protection, and power management

– Various stop, wait, and run modes to provide low

power based on application needs

– Peripheral clock enable register can disable clocks to

unused modules, thereby reducing currents

– Low voltage warning and detect with selectable trip

points

– Illegal opcode and illegal address detection with

programmable reset or processor exception response

– Hardware CRC module to support fast cyclic

redundancy checks (CRC)

– 128-bit unique chip identifier

– Hardware watchdog

– External Watchdog Monitor (EWM)

– Dual DMA controller with 32 channels (with

DMAMUX)

VYBRIDRSERIESEC

• Debug

– Standard JTAG

– 16-bit Trace port

• Timers

– Motor control/general purpose timer (FTM)

– Periodic Interrupt Timers (PITs)

– Low-power timer (LPTMR0)

– IEEE 1588 Timer per MAC interface (part of

Ethernet Subsystem)

• Communications

– Six Universal asynchronous receivers/transmitters

(UART)/Serial communications interface (SCI) with

LIN, ISO7816, IrDA, and hardware flow control

– Four Deserial Serial peripheral interface (DSPI)

– Four Inter-Integrated Circuit (I2C) with SMBUS

support

– Dual USB OTG Controller + PHY

– Dual 4/8 bit Secure Digital Host controller

– Local Media Bus (MLB50)

– Dual 10/100 Ethernet (IEEE 1588)

– Dual FlexCAN3

• Security

– ARM TrustZone including the TZ architecture

– Secure Non-Volatile Storage (SNVS)

– Real Time Clock

– Real Time Integrity Checker (RTIC)

– TrustZone Watchdog (TZ WDOG)

– Trust Zone Address Space Controller

– Random Number Generator

– Hashing

– Secure JTAG

• Memory Interfaces

– 8/16-bit DRAM Controller with support for

LPDDR2/DDR3 - Up to 400 MHz (ECC supported

for 8-bit only and not 16-bit)

– 8/16-bit NAND Flash controller with ECC (ECC

supported for 8-bit only and not 16-bit)

– Dual Quad SPI with XIP (Execute-In-Place)

– 8/16/32-bit External bus (Flexbus)

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

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