74ALVCH162601DGGS datasheet, PDF

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74ALVCH162601DGGS: DescriptionIC UNIV BUS TXRX 18BIT 56TSSOP; Categorylogic logic; File Size223KB，15 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com

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IC UNIV BUS TXRX 18BIT 56TSSOP

74ALVCH162601DGGS Parametric

Parameter Name	Attribute value
Brand Name	Nexperia
Maker	Nexperia
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	56
Manufacturer packaging code	SOT364-1
Reach Compliance Code	compliant
Samacsys Description	74ALVCH162601 - 18-bit universal bus transceiver with 30 ÃŽÂ© termination resistor;3-state@en-us
series	ALVC/VCX/A
JESD-30 code	R-PDSO-G56
JESD-609 code	e4
length	14 mm
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER
Humidity sensitivity level	2
Number of digits	18
Number of functions	1
Number of ports	2
Number of terminals	56
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE WITH SERIES RESISTOR
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	6.4 ns
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	2.4 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	6.1 mm
Base Number Matches	1

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74ALVCH162601

Rev. 2 — 13 August 2018

18-bit universal bus transceiver with 30 Ω termination

resistor; 3-state

Product data sheet

1. General description

The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting 3-state bus

compatible outputs in both send and receive directions. Data flow in each direction is controlled by

output enable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CPAB and CPBA)

inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.

When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is

LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When

OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance

state. The clocks can be controlled with the clock-enable inputs (CEBA and CEAB).

Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.

To ensure the high impedance state during power up or power down, OEBA and OEAB should

be tied to V

through a pullup resistor; the minimum value of the resistor is determined by the

current-sinking/current-sourcing capability of the driver.

The 74ALVCH162601 is designed with 30 Ω series resistors in both HIGH or LOW output stage.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

2. Features and benefits

•

CMOS low power consumption

MultiByte flow-through standard pin-out architecture

Low inductance multiple V

and GND pins for minimum noise and ground bounce

Direct interface with TTL levels

Bus hold on data inputs

Integrated 30 Ω termination resistors.

Complies with JEDEC standards:

•

JESD8-5 (2.3 V to 2.7 V)

•

JESD8B/JESD36 (2.7 V to 3.6 V)

ESD protection:

•

HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

•

CDM JESD22-C101E exceeds 1000 V

•

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range

74ALVCH162601DGG −40 °C to +85 °C

Name

TSSOP56

Description

plastic thin shrink small outline package;

56 leads; body width 6.1 mm

Version

SOT364-1

74ALVCH162601DGGS Related Products

	74ALVCH162601DGGS	74ALVCH162601DGG:1	74ALVCH162601DGGY
Description	IC UNIV BUS TXRX 18BIT 56TSSOP	74ALVCH162601 - 18-bit universal bus transceiver with 30 Ohm termination resistor; 3-state TSSOP 56-Pin	IC UNIV BUS TXRX 18BIT 56TSSOP
Brand Name	Nexperia	Nexperia	Nexperia
Parts packaging code	TSSOP	TSSOP	TSSOP
package instruction	TSSOP,	TSSOP,	TSSOP,
Contacts	56	56	56
Manufacturer packaging code	SOT364-1	SOT364-1	SOT364-1
Reach Compliance Code	compliant	unknown	compliant
series	ALVC/VCX/A	ALVC/VCX/A	ALVC/VCX/A
JESD-30 code	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56
length	14 mm	14 mm	14 mm
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER
Number of digits	18	18	18
Number of functions	1	1	1
Number of ports	2	2	2
Number of terminals	56	56	56
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR
Output polarity	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)	6.4 ns	6.4 ns	6.4 ns
Maximum seat height	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	1.2 V	1.2 V	1.2 V
Nominal supply voltage (Vsup)	2.4 V	2.4 V	2.4 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL
width	6.1 mm	6.1 mm	6.1 mm
Base Number Matches	1	1	1
Maker	Nexperia	-	Nexperia
Samacsys Description	74ALVCH162601 - 18-bit universal bus transceiver with 30 ÃŽÂ© termination resistor;3-state@en-us	-	74ALVCH162601 - 18-bit universal bus transceiver with 30 ÃŽÂ© termination resistor;3-state@en-us
JESD-609 code	e4	-	e4
Humidity sensitivity level	2	-	2
Peak Reflow Temperature (Celsius)	260	-	260
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	-	Nickel/Palladium/Gold (Ni/Pd/Au)
Maximum time at peak reflow temperature	30	-	30

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