DA14585
Bluetooth 5.0 SoC with Audio Interface
General Description
The DA14585 is an ultra-low power SoC integrating a 2.4 GHz transceiver and an
ARM Cortex-M0®
microcontroller with 96kB of RAM and 64kB of One-Time Programmable (OTP) memory. It offers a
very fast boot time (<50ms) and supports up to 8 BLE connections. It can be used as a standalone
application processor or as a data pump in hosted systems.
The radio transceiver, the baseband processor and the qualified
Bluetooth® LE
stack is fully
compliant with the
Bluetooth® Low Energy 5.0 standard.
The DA14585 has dedicated hardware for the Link Layer implementation of
Bluetooth® Low Energy
and interface controllers for enhanced connectivity capabilities.
The
Bluetooth® Low Energy
firmware includes the L2CAP service layer protocols, Security Manager
(SM), Attribute Protocol (ATT), the Generic Attribute Profile (GATT) and the Generic Access Profile
(GAP). All profiles published by the
Bluetooth
SIG as well as custom profiles are supported.
The device is suitable for remote control units (RCU) requiring support for voice commands, wireless
sensor nodes, Bluetooth Mesh applications, fitness trackers, toys and HID devices (keyboards, mice,
etc.).
Key Features
■
Complies with Bluetooth V5.0, ETSI EN 300
328 and EN 300 440 Class 2 (Europe), FCC
CFR47 Part 15 (US) and ARIB STD-T66
(Japan)
■
Supports up to 8 Bluetooth LE connections
■
Fast cold boot in less than 50 ms
■
Processing power
□
16 MHz 32 bit ARM Cortex-M0 with SWD
interface
■
Flexible Reset Circuitry
□
System & Power On Reset in a single pin
■
General purpose, Capture and Sleep timers
■
Digital interfaces
□
Gen. purpose I/Os: 14 (WLCSP34), 25
(QFN40), 32 (QFN48)
□
2 x UARTs with hardware flow control up
to 1 Mbps
□
Dedicated Link Layer Processor
□
AES-128 bit encryption Processor
■
Memories
□
64 kB One-Time-Programmable (OTP)
memory
□
SPI+™ interface
□
I2C bus at 100 kHz, 400 kHz
□
3-axes capable Quadrature Decoder
■
Analog interfaces
□
4-channel 10-bit ADC
■
Radio transceiver
□
Fully integrated 2.4 GHz CMOS
transceiver
□
96 kB Data/Retention SRAM
□
128 kB ROM
■
Power management
□
Integrated Buck/Boost DCDC converter
□
P0, P1 and P2 ports with 3.3 V tolerance
□
Easy decoupling of only 4 supply pins
□
Supports coin (typ. 3.0 V) and alkaline
(typ. 1.5 V) battery cells
□
Single wire antenna: no RF matching or
RX/TX switching required
□
Supply current at VBAT3V:
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-
DC)
□
1.8 V cold boot support
□
10-bit ADC for battery voltage
measurement
□
0 dBm transmit output power
□
-20 dBm output power in “Near Field
Mode”
□
-93 dBm receiver sensitivity
■
Digital controlled oscillators
□
16 MHz crystal (±20 ppm max) and RC
■
Packages:
□
WLCSP 34 pins, 2.40 mm x 2.66 mm
oscillator
□
QFN 40 pins, 5 mm x 5 mm
□
32 kHz crystal (±50 ppm, ±500 ppm max)
□
QFN 48 pins, 6 mm x 6 mm
and RCX oscillator
Revision 3.2
1 of 340
Datasheet
CFR0011-120-00
04-Apr-2018
© 2018 Dialog Semiconductor
DA14585
Bluetooth 5.0 SoC with Audio Interface
Applications
■
Voice-controlled remote controls
■
Beacons
■
(Multi-sensor) Wearable devices
□
Fitness trackers
□
Consumer health
■
Smartwatches
■
Human interface devices
□
Keyboard
□
Mouse
■
Toys
■
Consumer appliances
Key Benefits
■
Lowest power consumption
■
Smallest system size
■
Lowest system cost
System Diagram
Figure 1: System Diagram
Datasheet
CFR0011-120-00
Revision 3.2
2 of 340
04-Apr-2018
© 2018 Dialog Semiconductor
DA14585
Bluetooth 5.0 SoC with Audio Interface
Contents
General Description ............................................................................................................................ 1
Key Features ........................................................................................................................................ 1
Applications ......................................................................................................................................... 2
Key Benefits ......................................................................................................................................... 2
System Diagram .................................................................................................................................. 2
Contents ............................................................................................................................................... 3
Figures .................................................................................................................................................. 7
Tables ................................................................................................................................................... 8
1
2
3
The DA14585 Block Diagram...................................................................................................... 17
Pinout ........................................................................................................................................... 18
Specifications .............................................................................................................................. 23
3.1 Absolute Maximum Ratings ................................................................................................ 24
3.2 Recommended Operating Conditions ................................................................................. 25
3.3 DC Characteristics .............................................................................................................. 26
3.4 Timing Characteristics......................................................................................................... 27
3.5 16 MHz Crystal Oscillator Characteristics ........................................................................... 28
3.6 32 kHz Crystal Oscillator Characteristics ............................................................................ 29
3.7 Stable Low Frequency RCX Oscillator Characteristics ....................................................... 30
3.8 Digital Input/Output Characteristics .................................................................................... 30
3.9 General Purpose ADC Characteristics ............................................................................... 31
3.10 DC-DC Converter Characteristics ....................................................................................... 31
3.11 Radio Characteristics .......................................................................................................... 33
System Overview ......................................................................................................................... 37
4.1 Internal Blocks..................................................................................................................... 37
4.2 Functional Modes ................................................................................................................ 38
4.3 OTP Memory Layout ........................................................................................................... 38
4.3.1
OTP Header ......................................................................................................... 39
4.4 System Start Procedure ...................................................................................................... 42
4.4.1
Power/Wake-Up Sequence ................................................................................. 42
4.4.2
OTP Mirroring ...................................................................................................... 45
4.4.3
BootROM Sequence ............................................................................................ 45
4.5 Power Supply Configuration ............................................................................................... 48
4.5.1
Power Domains ................................................................................................... 48
4.5.2
Power Modes ....................................................................................................... 48
4.5.3
Retention Registers ............................................................................................. 49
4.5.4
Sleep LDO Voltage Trimming .............................................................................. 50
Reset ............................................................................................................................................. 51
5.1 POR, HW and SW Reset .................................................................................................... 51
5.1.1
Power-On Reset Functionality ............................................................................. 52
5.1.1.1
POR Timer Clock ............................................................................. 53
5.1.1.2
Reset Pad ........................................................................................ 53
5.1.1.3
POR from GPIO ............................................................................... 53
5.1.2
Power-On Reset Timing Diagram ........................................................................ 53
Revision 3.2
3 of 340
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5
Datasheet
CFR0011-120-00
04-Apr-2018
© 2018 Dialog Semiconductor
DA14585
Bluetooth 5.0 SoC with Audio Interface
5.1.3
6
Power-On Reset Considerations ......................................................................... 54
ARM Cortex-M0 ............................................................................................................................ 55
6.1 Interrupts ............................................................................................................................. 56
6.2 System Timer (systick) ........................................................................................................ 58
6.3 Wake-Up Interrupt Controller .............................................................................................. 58
6.4 Reference ............................................................................................................................ 58
AMBA Bus Overview ................................................................................................................... 59
Patch Block .................................................................................................................................. 60
Memory Map................................................................................................................................. 62
7
8
9
10 Memory Controller ...................................................................................................................... 64
10.1 Arbitration ............................................................................................................................ 65
11 Clock Generation ......................................................................................................................... 66
11.1 Crystal Oscillators ............................................................................................................... 66
11.1.1 Frequency Control (16 MHz Crystal) ................................................................... 66
11.1.2 Automated Trimming Mechanism ........................................................................ 67
11.2 RC Oscillators ..................................................................................................................... 67
11.2.1 Frequency Calibration .......................................................................................... 68
11.3 System Clock Generation ................................................................................................... 68
11.4 General Clock Constraints .................................................................................................. 70
12 OTP Controller ............................................................................................................................. 71
12.1 Introduction ......................................................................................................................... 71
12.2 Operating Modes ................................................................................................................. 71
12.3 AHB Master Interface .......................................................................................................... 72
12.4 AHB Slave Interface ............................................................................................................ 72
12.5 Error Correcting Code (ECC) .............................................................................................. 73
12.6 BUILD-IN Self Repair (BISR) .............................................................................................. 73
13 DMA controller ............................................................................................................................. 74
13.1 DMA Peripherals ................................................................................................................. 74
13.2 Input/Output Multiplexer ...................................................................................................... 75
13.3 DMA Channel Operation ..................................................................................................... 75
13.4 DMA Arbitration ................................................................................................................... 76
13.5 Freezing DMA channels ...................................................................................................... 77
14 I2C Interface ................................................................................................................................. 78
14.1 I2C Bus Terms .................................................................................................................... 79
14.1.1 Bus Transfer Terms ............................................................................................. 79
14.2 I2C Behavior ....................................................................................................................... 80
14.2.1 START and STOP Generation ............................................................................ 80
14.2.2 Combined Formats .............................................................................................. 81
14.3 I2C Protocols ....................................................................................................................... 81
14.3.1 START and STOP Conditions ............................................................................. 81
14.3.2 Addressing Slave Protocol................................................................................... 81
14.3.3 Transmitting and Receiving Protocols ................................................................. 82
14.4 Multiple Master Arbitration .................................................................................................. 84
14.5 Clock Synchronization......................................................................................................... 85
14.6 Operation Modes ................................................................................................................. 85
Datasheet
CFR0011-120-00
Revision 3.2
4 of 340
04-Apr-2018
© 2018 Dialog Semiconductor
DA14585
Bluetooth 5.0 SoC with Audio Interface
14.6.1 Slave Mode Operation ......................................................................................... 86
14.6.2 Master Mode Operation ....................................................................................... 88
14.7 Disabling the I2C Controller ................................................................................................ 89
15 UART ............................................................................................................................................. 90
15.1 UART (RS232) Serial Protocol ........................................................................................... 91
15.2 IrDA 1.0 SIR Protocol .......................................................................................................... 92
15.3 Clock Support ...................................................................................................................... 93
15.4 Interrupts ............................................................................................................................. 93
15.5 Programmable THRE Interrupt ........................................................................................... 94
15.6 Shadow Registers ............................................................................................................... 96
15.7 Direct Test Mode ................................................................................................................. 96
16 SPI+ Interface............................................................................................................................... 97
16.1 Operation without FIFOs ..................................................................................................... 98
16.2 9 Bits Mode ......................................................................................................................... 99
16.3 SPI Timing ......................................................................................................................... 100
17 Quadrature Decoder .................................................................................................................. 102
18 Wake-Up Timer .......................................................................................................................... 104
19 General Purpose Timers ........................................................................................................... 105
19.1 Timer 0 .............................................................................................................................. 105
19.2 Timer 2 .............................................................................................................................. 108
20 Watchdog Timer ........................................................................................................................ 110
21 Keyboard Controller .................................................................................................................. 112
21.1 Keyboard Scanner ............................................................................................................ 112
21.2 GPIO Interrupt Generator.................................................................................................. 113
22 Input/Output Ports ..................................................................................................................... 115
22.1 Programmable Pin Assignment ........................................................................................ 115
22.2 General Purpose Port Registers ....................................................................................... 116
22.2.1 Port Data Register ............................................................................................. 116
22.2.2 Port Set Data Output Register ........................................................................... 116
22.2.3 Port Reset Data Output Register ....................................................................... 116
22.3 Fixed Assignment Functionality ........................................................................................ 116
23 General Purpose ADC ............................................................................................................... 118
23.1 Input Channels and Input Scale ........................................................................................ 118
23.2 Starting the ADC and Sampling Rate ............................................................................... 119
23.3 Non-Ideal Effects............................................................................................................... 119
23.4 Chopping ........................................................................................................................... 119
23.5 Offset Calibration .............................................................................................................. 120
23.6 Zero-Scale Adjustment...................................................................................................... 120
23.7 Common Mode Adjustment .............................................................................................. 121
23.8 Input Impedance, Inductance and Input Settling .............................................................. 121
23.9 Delay Counter ................................................................................................................... 122
24 Audio Unit (AU) .......................................................................................................................... 123
24.1 Introduction ....................................................................................................................... 123
24.2 Architecture ....................................................................................................................... 124
24.2.1 Data Paths ......................................................................................................... 124
Datasheet
CFR0011-120-00
Revision 3.2
5 of 340
04-Apr-2018
© 2018 Dialog Semiconductor
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