SLG7NT4129
PCIE RTD3
General Description
Silego SLG7NT4129 is a low power and small form
device. The SoC is housed in a 2.5mm x 2.5mm
TDFN package which is optimal for using with small
devices.
Pin Configuration
VDD
PWR_CNTRL_GPIO#
PLT_RST#
DEVICE_WAKE#
RST_CNTRL_GPIO#
NC
1
2
3
4
5
6
SLG7NT4129
12
11
10
9
8
7
DEVICE_RESET#
PCIE_WAKE#
NC
WAKE_GPIO
Features
• Low Power Consumption
• Dynamic Supply Voltage
• RoHS Compliant / Halogen-Free
• Pb-Free TDFN-12 Package
NC
GND
TDFN-12
TOP VIEW
Thermal Pad
connected to GND
Output Summary
• 2 Outputs – Open Drain
• 2 Outputs – 3-State
Block Diagram
Silego Technology, Inc.
SLG7NT4129_DS_r101
SLG7NT4129_GP_r004
Rev 1.01
Revised June 11, 2013
SLG7NT4129
PCIE RTD3
Pin Configuration
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
Exposed
Bottom Pad
Pin Name
VDD
PWR_CNTRL_GPIO#
PLT_RST#
DEVICE_WAKE#
RST_CNTRL_GPIO#
NC
GND
NC
WAKE_GPIO
NC
PCIE_WAKE#
DEVICE_RESET#
Exposed Bottom Pad
Type
PWR
Input
Input
Input/Output
Input
--
GND
--
Output
--
Input/Output
Output
GND
Pin Description
Supply Voltage
Digital Input
Digital Input
3-State
Digital Input
Keep floating or connect to GND
Ground
Keep floating or connect to GND
Open Drain
Keep floating or connect to GND
3-State
Open Drain
Ground
Ordering Information
Part Number
SLG7NT4129V
SLG7NT4129VTR
Package Type
V = TDFN-12
VTR = TDFN-12 - Tape and Reel (3k units)
SLG7NT4129_DS_r101
Page 2
SLG7NT4129
PCIE RTD3
Absolute Maximum Conditions
Parameter
V
HIGH
to GND
Voltage at input pins
Current at input pin
Storage temperature range
Junction temperature
Min.
-0.3
-0.3
-1.0
-65
--
Max.
7
7
1.0
150
150
Unit
V
V
mA
°C
°C
Electrical Characteristics
(@ 25°C, unless otherwise stated)
Symbol Parameter
V
DD
I
Q
T
A
I
L
V
IH
V
IL
I
IH
I
IL
T
DLY0
V
OH
Supply Voltage
Quiescent Current
Operating Temperature
Input Leakage Current
HIGH-Level Input Voltage
LOW-Level Input Voltage
HIGH-Level Input Current
LOW-Level Input Current
Delay0 Time
Output Voltage High
Condition/Note
Static inputs and outputs
Leakage Current for Digital Inputs or
outputs in High impedance state
Logic Input, at VDD=1.8V
Logic Input, at VDD=3.3V
Logic Input, at VDD=1.8V
Logic Input, at VDD=3.3V
Logic Input Pins; V
IN
=VDD
Logic Input Pins; V
IN
=0V
3-State, OE=1, I
OH
= 100µA at VDD=1.8V
3-State, OE=1, I
OH
= 3mA at VDD=3.3V
3-State, OE=1, I
OL
= 100µA at VDD=1.8V
3-State, OE=1, I
OL
= 3mA at VDD=3.3V
Min.
1.71
--
-40
-100
1.1
1.8
--
-1
-1
2.1
1.66
2.1
--
--
--
--
--
Typ.
--
1
25
--
--
--
Max.
3.6
--
85
100
--
0.65
1.1
1
1
Unit
V
μA
°C
nA
V
V
μA
μA
ms
V
3
--
--
--
--
--
--
--
--
--
--
--
7
3.9
--
--
0.04
0.81
0.340
0.605
VDD
--
--
--
--
--
V
OL
Output Voltage Low
Open Drain, I
OL
= 5mA, at VDD=1.8V
Open Drain, I
OL
= 20mA at VDD=3.3V
V
V
O
Maximal Voltage Applied to any
PIN in High-Impedance State
3-State, OE=1, V
OL
=0.15V, at VDD=1.8V
3-State, OE=1, V
OL
= 0.4V, at VDD=3.3V
Open Drain, V
OL
=0.15V, at VDD=1.8V
Open Drain, V
OL
= 0.4V, at VDD=3.3V
After VDD reaches 1.6V level
V
0.34
1.836
2.7
14.6
--
I
OL
LOW-Level Output Current
mA
T
SU
Start up Time
ms
SLG7NT4129_DS_r101
Page 3
京公网安备 11010802033920号
EEWORLD
