ISL12024IRTCZ-T datasheet, PDF

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DATASHEET

ISL12024IRTC

Real-Time Clock/Calendar with Embedded Unique ID

The ISL12024IRTCZ device is a micro-power real-time clock

with embedded 64-bit unique ID, timing and crystal

compensation, clock/calender, power-fail indicator, two

periodic or polled alarms, intelligent battery backup

switching, and integrated 512x8-bit EEPROM configured in

16 Bytes per page.

The device contains a 64-bit unique ID number for security

and product identification applications. It is housed in a tiny

3mmx3mm TDFN package for small handheld applications.

The clock output defaults to 32.768kHz on initial power-up

for low power microcontroller clocking applications. The low

800nA battery supply current extends backup battery life.

FN6749

Rev 1.00

December 15, 2011

Features

• Real-Time Clock/Calendar

- Tracks Time in Hours, Minutes, and Seconds

- Day of the Week, Day, Month and Year

- 3 Selectable Frequency Outputs

• 64-Bit Unique ID

• Two Non-Volatile Alarms

- Settable on the Second, Minute, Hour, Day of the Week,

Day or Month

- Repeat Mode (Periodic Interrupts)

• Automatic Backup to Battery or Super Cap

• Default 32.768kHz Output at IRQ/F

OUT

(FO1 = 0, FO0 = 1)

Ordering Information

TEMP

RANGE

PART NUMBER

PART

V

DD

(°C)

(Note)

MARKING RANGE

ISL12024IRTCZ* 024C

PACKAGE PKG.

(Pb-Free) DWG. #

2.7V to -40 to +85 8 Ld TDFN L8.3x3I

5.5V

• On-Chip Oscillator Compensation

- Internal Feedback Resistor and Compensation

Capacitors

- 64 Position Digitally Controlled Trim Capacitor

- 6 Digital Frequency Adjustment Settings to ±30ppm

• 512x8-Bits of EEPROM

- 16-Bytes Page Write Mode (32 total pages)

- 8 Modes of BlockLock™ Protection

- Single Byte Write Capability

• High Reliability

- Data Retention: 50 years

- Endurance: 2,000,000 Cycles Per Byte

• I

2

C Interface

- 400kHz Data Transfer Rate

*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel

specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special

Pb-free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is RoHS

compliant and compatible with both SnPb and Pb-free soldering

operations). Intersil Pb-free products are MSL classified at Pb-free peak

reflow temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

Pinout

ISL12024IRTCZ

(8 LD TDFN)

TOP VIEW

X1

X2

IRQ/F

OUT

GND

1

2

3

4

8

7

6

5

VDD

VBAT

SCL

SDA

• 800nA Battery Supply Current

• Available in 8 Ld TDFN package

• Pb-Free (RoHS Compliant)

Applications

• Utility Meters

• Audio Video Equipment

• Modems

• Network Routers, Hubs, Switches, Bridges

• Cellular Infrastructure Equipment

• Fixed Broadband Wireless Equipment

• Pagers/PDA

• POS Equipment

• Test Meters/Fixtures

• Office Automation (Copiers, Fax)

• Computer Products

• Security Related Application

FN6749 Rev 1.00

December 15, 2011

Page 1 of 24

ISL12024IRTC

Block Diagram

OSC

COMPENSATION

X1

X2

IRQ/F

OUT

SELECT

CONTROL/

REGISTERS

(EEPROM)

STATUS

REGISTERS

(SRAM)

TIMER

FREQUENCY 1Hz

CALENDAR

DIVIDER

LOGIC

TIME

KEEPING

REGISTERS

(SRAM)

BATTERY

SWITCH

CIRCUITRY

VDD

VBAT

32.768kHz

OSCILLATOR

SCL

SDA

MASK

SERIAL

INTERFACE

DECODER

CONTROL

DECODE

LOGIC

ALARM

COMPARE

ALARM REGS

(EEPROM)

4k

EEPROM

ARRAY

8

Pin Descriptions

NUMBER

TDFN

1

2

3

4

5

6

7

8

SYMBOL

X1

X2

IRQ/F

OUT

GND

SDA

SCL

VBAT

VDD

DESCRIPTION

The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz

quartz crystal.

The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz

quartz crystal. (See “Application Section” on page 20.)

Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. The

function is set via the control register. This output is an open drain configuration.

Ground.

Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain

output and may be wire OR’ed with other open drain or open collector outputs.

The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is

always active (not gated).

This input provides a backup supply voltage to the device. V

BAT

supplies power to the device in the event that the

V

DD

supply fails. This pin should be tied to ground if not used.

Power Supply.

FN6749 Rev 1.00

December 15, 2011

Page 2 of 24

ISL12024IRTC

Absolute Maximum Ratings

Voltage on V

DD

, V

BAT

, SCL, SDA, and

IRQ/F

OUT

Pins

(Respect to Ground). . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Voltage on X1 and X2 Pins

(Respect to Ground). . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V

Latchup (Note 1) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C

ESD Rating (MIL-STD-883, Method 3014) . . . . . . . . . . . . . . .>±2kV

ESD Rating (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . .>175V

Thermal Information

Thermal Resistance (Typical, Notes 1, 2)



JA

(°C/W)



JC

(°C/W)

TDFN Package . . . . . . . . . . . . . . . .

53.7

2.8

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1.



JA

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

2. For



JC

, the “case temp” location is the center of the exposed metal pad on the package underside.

Operating Specifications

Unless otherwise noted, V

DD

= +2.7V to +5.5V, T

A

= -40°C to +85°C, Typical values are @ T

A

= +25°C and

V

DD

= 3.3V.

MIN

(Note 12)

2.7

1.8

MAX

(Note 12)

5.5

SYMBOL

V

DD

V

BAT

PARAMETER

Main Power Supply

Backup Power Supply

CONDITIONS

TYP

UNIT

V

Electrical Specifications

SYMBOL

I

DD1

PARAMETER

Supply Current with I

2

C Active

V

DD

= 2.7V

V

DD

= 5.5V

I

DD2

Supply Current for Non-Volatile

Programming

Supply Current for Main Timekeeping

(Low Power Mode)

Battery Supply Current

V

DD

= 2.7V

V

DD

= 5.5V

V

DD

= V

SDA

= V

SCL

= 2.7V

V

DD

= V

SDA

= V

SCL

= 5.5V

V

BAT

= 1.8V, V

DD

= V

SDA

= V

SCL

= 0V

V

BAT

= 3.0V, V

DD

= V

SDA

= V

SCL

= 0V

I

BATLKG

V

TRIP

V

TRIPHYS

V

BATHYS

V

DD SR-

IRQ/F

OUT

V

OL

Output Low Voltage

V

DD

= 5V

I

OL

= 3mA

V

DD

= 1.8V

I

OL

= 1mA

I

LO

Output Leakage Current

V

DD

= 5.5V

V

OUT

= 5.5V

100

0.4

400

V

nA

Battery Input Leakage

V

BAT

Mode Threshold

V

TRIP

Hysteresis

V

BAT

Hysteresis

V

DD

Negative Slew Rate

V

DD

= 5.5V, V

BAT

= 1.8V

1.8

2.2

30

50

10

800

850

CONDITIONS

MIN

(Note 12)

TYP

MAX

(Note 12)

500

800

2.5

3.5

10

20

1000

1200

100

2.6

UNIT

µA

mA

µA

nA

V

mV

V/ms

7

8

NOTES

3, 4, 5

5

3, 6, 7

I

DD3

I

BAT

FN6749 Rev 1.00

December 15, 2011

Page 3 of 24

ISL12024IRTC

EEPROM Specifications

PARAMETER

EEPROM Endurance

EEPROM Retention

Temperature

75°C

TEST CONDITIONS

MIN

2,000,000

50

TYP

MAX

UNITS

Cycles

Years

Serial Interface (I

2

C) Specifications

DC Electrical Specifications

SYMBOL

V

IL

V

IH

Hysteresis

V

OL

I

LI

I

LO

PARAMETER

SDA, and SCL Input Buffer LOW

Voltage

SDA, and SCL Input Buffer HIGH

Voltage

SDA and SCL Input Buffer Hysteresis

SDA Output Buffer LOW Voltage

Input Leakage Current on SCL

I/O Leakage Current on SDA

I

OL

= 4mA

V

IN

= 5.5V

V

IN

= 5.5V

TEST CONDITIONS

MIN

(Note 12)

-0.3

0.7 x V

DD

0.05 x V

DD

0

100

0.4

TYP

MAX

(Note 12)

0.3 x V

DD

V

DD

+ 0.3

UNITS

V

nA

9, 11

NOTES

AC Electrical Specifications

SYMBOL

f

SCL

t

IN

t

AA

t

BUF

PARAMETER

SCL Frequency

Pulse width Suppression Time at

SDA and SCL Inputs

SCL Falling Edge to SDA Output

Data Valid

Time the Bus Must be Free Before

the Start of a New Transmission

Clock LOW Time

Clock HIGH Time

START Condition Set-up Time

START Condition Hold Time

Input Data Set-up Time

Any pulse narrower than the max spec is

suppressed.

SCL falling edge crossing 30% of V

DD

, until

SDA exits the 30% to 70% of V

DD

window.

SDA crossing 70% of V

DD

during a STOP

condition, to SDA crossing 70% of V

DD

during

the following START condition.

Measured at the 30% of V

DD

crossing.

Measured at the 70% of V

DD

crossing.

SCL rising edge to SDA falling edge. Both

crossing 70% of V

DD

.

From SDA falling edge crossing 30% of V

DD

to

SCL falling edge crossing 70% of V

DD

.

From SDA exiting the 30% to 70% of V

DD

window, to SCL rising edge crossing 30% of

V

DD

.

From SCL rising edge crossing 70% of V

DD

to

SDA entering the 30% to 70% of V

DD

window.

From SCL rising edge crossing 70% of V

DD

, to

SDA rising edge crossing 30% of V

DD

.

From SDA rising edge to SCL falling edge. Both

crossing 70% of V

DD

.

From SCL falling edge crossing 30% of V

DD

,

until SDA enters the 30% to 70% of V

DD

window.

1300

TEST CONDITIONS

MIN

(Note 12)

MAX

TYP (Note 12) UNITS NOTES

400

50

900

kHz

ns

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

t

SU:DAT

1300

600

100

ns

t

HD:DAT

t

SU:STO

t

HD:STO

t

DH

Input Data Hold Time

STOP Condition Set-up Time

STOP Condition Hold Time for

Read, or Volatile Only Write

Output Data Hold Time

0

600

0

ns

FN6749 Rev 1.00

December 15, 2011

Page 4 of 24

ISL12024IRTC

AC Electrical Specifications

SYMBOL

Cpin

t

WC

t

R

t

F

Cb

R

PU

PARAMETER

SDA and SCL Pin Capacitance

Non-Volatile Write Cycle Time

SDA and SCL Rise Time

SDA and SCL Fall Time

From 30% to 70% of V

DD

From 70% to 30% of V

DD

20+0.1xCb

10

1

12

(Continued)

TEST CONDITIONS

MIN

(Note 12)

MAX

TYP (Note 12) UNITS NOTES

10

20

300

400

pF

ms

ns

pF

k

9, 11

10

9, 11

Capacitive Loading of SDA or SCL Total on-chip and off-chip.

SDA and SCL Bus Pull-up Resistor Maximum is determined by t

R

and t

F

.

Off-chip

For Cb = 400pF, max is about 2k~2.5k.

For Cb = 40pF, max is about 15k~20k

NOTES:

3. IRQ/F

OUT

Inactive.

4. V

IL

= V

DD

x 0.1, V

IH

= V

DD

x 0.9, f

SCL

= 400kHz

5. V

DD

> V

BAT

+V

BATHYS

6. Bit BSW = 0 (Standard Mode), ATR = 00h, V

BAT

1.8V

7. Specified at +25°C.

8. In order to ensure proper timekeeping, the V

DD SR-

specification must be followed.

9. Limits established by characterization and are not production tested.

10. t

WC

is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end of Write

sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.

11. These are I

2

C specific parameters and are not directly tested, however they are used during device testing to validate device specification.

12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

Timing Diagrams

Bus Timing

t

F

t

HIGH

t

LOW

t

R

t

HD:STO

SCL

t

SU:STA

SDA

(INPUT TIMING)

t

SU:DAT

t

HD:DAT

t

SU:STO

t

HD:STA

t

AA

SDA

(OUTPUT TIMING)

t

DH

t

BUF

Write Cycle Timing

SCL

SDA

8TH BIT OF LAST BYTE

ACK

t

WC

STOP

CONDITION

START

CONDITION

FN6749 Rev 1.00

December 15, 2011

Page 5 of 24

Parameter Name	Attribute value
Brand Name	Intersil
Maker	Renesas Electronics Corporation
Parts packaging code	DFN
package instruction	HVSON, SOLCC8,.12,25
Contacts	8
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	8 weeks
maximum clock frequency	0.032 MHz
Information access methods	I2C
interrupt capability	Y
JESD-30 code	S-PDSO-N8
JESD-609 code	e3
length	3 mm
Humidity sensitivity level	1
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	HVSON
Encapsulate equivalent code	SOLCC8,.12,25
Package shape	SQUARE
Package form	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	0.8 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	2.7 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	NO LEAD
Terminal pitch	0.65 mm
Terminal location	DUAL
shortest time	SECONDS
Maximum time at peak reflow temperature	NOT SPECIFIED
Volatile	NO
width	3 mm
uPs/uCs/peripheral integrated circuit type	TIMER, REAL TIME CLOCK

	ISL12024IRTCZ-T
Description	IC RTC CLK/CALENDAR I2C 8-TDFN
Brand Name	Intersil
Maker	Renesas Electronics Corporation
Parts packaging code	DFN
package instruction	HVSON, SOLCC8,.12,25
Contacts	8
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	8 weeks
maximum clock frequency	0.032 MHz
Information access methods	I2C
interrupt capability	Y
JESD-30 code	S-PDSO-N8
JESD-609 code	e3
length	3 mm
Humidity sensitivity level	1
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	HVSON
Encapsulate equivalent code	SOLCC8,.12,25
Package shape	SQUARE
Package form	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	0.8 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	2.7 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	NO LEAD
Terminal pitch	0.65 mm
Terminal location	DUAL
shortest time	SECONDS
Maximum time at peak reflow temperature	NOT SPECIFIED
Volatile	NO
width	3 mm
uPs/uCs/peripheral integrated circuit type	TIMER, REAL TIME CLOCK

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