DSC400-0103Q0102KI1 datasheet, PDF

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DSC400-0103Q0102KI1: Description148.5LVDSX1,14.7456LVCMOSX1, -40; CategoryPassive components; File Size2MB，11 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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DSC400-0103Q0102KI1 Overview

148.5LVDSX1,14.7456LVCMOSX1, -40

DSC400-0103Q0102KI1 Parametric

Parameter Name	Attribute value
type	MEMS (silicon)
Frequency - Output 1	148.5MHz
Frequency - Output 2	14.7456MHz
Frequency - Output 3	-
Frequency - Output 4	-
Function	enable/disable
output	LVCMOS，LVDS
Voltage - Power	2.25 V ~ 3.6 V
frequency stability	±50ppm
Operating temperature	-40°C ~ 85°C
Current - Power (maximum)	44mA
size/dimensions	0.197" long x 0.126" wide (5.00mm x 3.20mm)
high	0.035"（0.90mm）
Package/casing	20-SMD, no leads

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DSC400-0103Q0102

Crystal-less™ Configurable Clock Generator

General Description

The DSC400-0103Q0102 is a four output

crystal-less™ clock generator. It utilizes Microchip's

proven PureSilicon™ MEMS technology to provide

excellent jitter and stability while incorporating

additional device functionality.

The frequencies of the outputs can be identical or

independently derived from two shared PLLs. Each

output may be configured independently to support

LVCMOS, LVPECL, LVDS, or HCSL output

standards.

The DSC400-0103Q0102 provides two independent

select lines for choosing between two sets of pre-

configured frequencies per bank. It also has two OE

pins to allow for enabling and disabling outputs.

Features

• Frequencies and output formats:

- 148.5MHz LVDS x 1

- 14.7456MHz LVCMOS x 1

• Low RMS phase jitter: <1ps (typ)

• High stability: ±25ppm, ±50ppm

• Wide temperature range

- Industrial: -40°C to +85°C

- Ext. commercial: -20°C to +70°C

• High supply noise rejection: -50dBc

• Available pin-selectable frequency table

- 1 pin per bank for 2 frequency sets

• Excellent shock & vibration immunity

- Qualified to MIL-STD-883

• High reliability

- 20x better MTF than quartz based devices

• Supply range of 2.25V to 3.6V

• AEC-Q100 automotive qualified

• 20-pin 5mm x 3.2mm QFN package

Applications

• Communications and Networks

• Ethernet

- 1G, 10GBASE-T/KR/LR/SR, and FCoE

• Storage Area Networks

- SATA, SAS, Fibre Channel

• Passive Optical Networks

- EPON, 10G-EPON, GPON, 10G-GPON

• HD/SD/SDI Video & Surveillance

• Automotive

• Media and Video

• Embedded and Industrial

Block Diagram

Control Circuitry

Output

Control

And

Dividers

VDD1/VDD2

MEMS

OE1

FSB1

PLL

CLK1+

148.5MHz LVDS

CLK1-

Control Circuitry

Output

Control

And

Dividers

CLK3

14.7456MHz LVCMOS

MEMS

OE2

FSB2

PLL

ClockWorks is a registered trademark of Microchip Technology Inc.

Microchip Technology Inc.

VSS

http://www.microchip.com

June 21, 2017

5401

Revision 1.0

tcghelp@microchip.com

Microchip Technology Inc.

DSC400-0103Q0102

Operational Description

The DSC400-0103Q0102 is a crystal-less™ clock generator. Unlike older clock generators in the industry, it does not require an

external crystal to operate; it relies on integrated MEMS resonators that interface with internal PLLs. This technology enhances

performance and reliability by allowing tighter frequency stability over a far wider temperature range. In addition, the higher

resistance to shock and vibration decreases the aging rate, greatly improving product life in the system.

Inputs

There are 4 input signals in the device. Each has an internal (40kOhms) pull up, which defaults the selection to a high (1). Inputs

can be controlled through hardware strapping method with a resistor to ground to assert the input low (0). Inputs may also be

controlled by other components' GPIOs. In case more than one frequency set is desired, FSB1 and FSB2 are used for independent-

ly selecting one of two sets frequency per bank. FSB1 selects the pre-configured frequency set on Bank 1 (CLK1 and CLK4) and

FSB2 selects the pre-configured frequency set on Bank 2 (CLK3 and CLK2). If there is a requirement to disable outputs, the

inputs OE1 and OE2 are used to disable the banks of outputs. Outputs are disabled in tristate (Hi-Z) mode, see Table 1 below.

OE1

OE2

Bank 1 (CLK1 and CLK4)

Hi-Z

Running

Table 1. Output Enable (OE) Selection Table

Bank 2 (CLK3 and CLK2)

Hi-Z

Running

Hi-Z

Running

Outputs

The four outputs are grouped into two banks. Each bank is supplied by an independent VDD to allow for optimized noise

isolation between the two banks. Each bank provides two synchronous outputs generated by a common PLL:

• Bank 1 is composed of outputs CLK1 and CLK4

• Bank 2 is composed of outputs CLK3 and CLK2

Each output maybe pre-configured independently to be one of the following formats: LVCMOS, LVDS, LVPECL or HCSL.

In case the output is configured to be single ended (LVCMOS only), the frequency is generated on the true output (CLKx+) and

the complement output (CLKx-) is shut off in a low state. Frequencies can be chosen from 2.3MHz to 460MHz for differential

outputs and from 2.3MHz to 170MHz on LVCMOS outputs.

Output Clock Frequencies

Output

Frequency (MHz)

CLK1

148.5

CLK2

CLK3

14.7456

CLK4

Power

VDD1 and VDD2 supply the power to banks 1 and 2 respectively. Each VDD may have different supply voltage from the other

as long as it is within the 2.25V to 3.6V range. Each VDD pin should have a 0.1µF capacitor to filter high frequency noise.

VSS is common to the entire device. The exposed die paddle should be connected to VSS.

June 21, 2017

5401

Revision 1.0

tcghelp@microchip.com

DSC400-0103Q0102KI1 Related Products

	DSC400-0103Q0102KI1	DSC400-0103Q0102KE1	DSC400-0103Q0102KE2	DSC400-0103Q0102KI2	DSC400-0103Q0102KE1T	DSC400-0103Q0102KE2T	DSC400-0103Q0102KI1T	DSC400-0103Q0102KI2T
Description	148.5LVDSX1,14.7456LVCMOSX1, -40	148.5LVDSX1,14.7456LVCMOSX1, -20	148.5LVDSX1,14.7456LVCMOSX1, -20	148.5LVDSX1,14.7456LVCMOSX1, -40	148.5LVDSX1,14.7456LVCMOSX1, -20	148.5LVDSX1,14.7456LVCMOSX1, -20	148.5LVDSX1,14.7456LVCMOSX1, -40	148.5LVDSX1,14.7456LVCMOSX1, -40
type	MEMS (silicon)	MEMS (silicon)	MEMS (silicon)	MEMS (silicon)	MEMS (silicon)	MEMS (silicon)	MEMS (silicon)	MEMS (silicon)
Frequency - Output 1	148.5MHz	148.5MHz	148.5MHz	148.5MHz	148.5MHz	148.5MHz	148.5MHz	148.5MHz
Frequency - Output 2	14.7456MHz	14.7456MHz	14.7456MHz	14.7456MHz	14.7456MHz	14.7456MHz	14.7456MHz	14.7456MHz
Function	enable/disable	enable/disable	enable/disable	enable/disable	enable/disable	enable/disable	enable/disable	enable/disable
output	LVCMOS，LVDS	LVCMOS，LVDS	LVCMOS，LVDS	LVCMOS，LVDS	LVCMOS，LVDS	LVCMOS，LVDS	LVCMOS，LVDS	LVCMOS，LVDS
Voltage - Power	2.25 V ~ 3.6 V	2.25 V ~ 3.6 V	2.25 V ~ 3.6 V	2.25 V ~ 3.6 V	2.25 V ~ 3.6 V	2.25 V ~ 3.6 V	2.25 V ~ 3.6 V	2.25 V ~ 3.6 V
frequency stability	±50ppm	±50ppm	±25ppm	±25ppm	±50ppm	±25ppm	±50ppm	±25ppm
Operating temperature	-40°C ~ 85°C	-20°C ~ 70°C	-20°C ~ 70°C	-40°C ~ 85°C	-20°C ~ 70°C	-20°C ~ 70°C	-40°C ~ 85°C	-40°C ~ 85°C
Current - Power (maximum)	44mA	44mA	44mA	44mA	44mA	44mA	44mA	44mA
size/dimensions	0.197" long x 0.126" wide (5.00mm x 3.20mm)	0.197" long x 0.126" wide (5.00mm x 3.20mm)	0.197" long x 0.126" wide (5.00mm x 3.20mm)	0.197" long x 0.126" wide (5.00mm x 3.20mm)	0.197" long x 0.126" wide (5.00mm x 3.20mm)	0.197" long x 0.126" wide (5.00mm x 3.20mm)	0.197" long x 0.126" wide (5.00mm x 3.20mm)	0.197" long x 0.126" wide (5.00mm x 3.20mm)
high	0.035"（0.90mm）	0.035"（0.90mm）	0.035"（0.90mm）	0.035"（0.90mm）	0.035"（0.90mm）	0.035"（0.90mm）	0.035"（0.90mm）	0.035"（0.90mm）
Package/casing	20-SMD, no leads	20-SMD, no leads	20-SMD, no leads	20-SMD, no leads	20-SMD, no leads	20-SMD, no leads	20-SMD, no leads	20-SMD, no leads

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