Enpirion
®
Power Datasheet
EN5311QI 1A PowerSoC
Synchronous Buck Regulator
With Integrated Inductor
Featuring Integrated Inductor Technology
V
IN
Product Overview
The Ultra-Low-Profile EN5311QI is targeted to
applications where board area and profile are
critical. EN5311QI is a complete power
conversion solution requiring only two low cost
ceramic MLCC caps. Inductor, MOSFETS,
PWM, and compensation are integrated into a
tiny 5mm x 4mm x 1.1mm QFN package. The
EN5311QI is engineered to simplify design and
to minimize layout constraints.
4 MHz
switching frequency and internal type III
compensation provides superior transient
response.
With a 1.1 mm profile, the
EN5311QI is ideal for space and height
constrained applications.
A 3-pin VID output voltage selector provides
seven pre-programmed output voltages along
with an option for external resistor divider.
Output voltage can be programmed on-the-fly
to provide fast, dynamic voltage scaling.
UVLO
Thermal Limit
Current Limit
ENABLE
Soft Start
P-Drive
(-)
PWM
Comp
(+)
Logic
N-Drive
V
OUT
GND
Sawtooth
Generator
Compensation
Network
V
SENSE
(-)
Error
Amp
(+)
Switch
V
FB
DAC
VREF
Voltage
Select
Package Boundry
VS0 VS1 VS2
Product Highlights
•
Revolutionary Integrated Inductor
•
5mm x 4mm x1.1mm QFN package
•
Very small total solution foot print*
•
4 MHz switching frequency
•
Only two low cost MLCC caps required
•
Designed for low noise/low EMI
•
Very low ripple voltage; 5mV
p-p
Typical
•
High efficiency, up to 95%
•
Wide 2.4V to 6.6V input range
•
1000mA continuous output current
•
Less than 1
µA
standby current.
•
Excellent transient performance
•
3 Pin VID Output Voltage select
•
External divider: 0.6V to V
IN
-V
dropout
•
100% duty cycle capable
•
Short circuit and over current protection
•
UVLO and thermal protection
•
RoHS compliant; MSL 3 260°C reflow
Typical Application Circuit
V
IN
4.7µF
ENABLE VSENSE
VIN
VOUT
C
OUT
V
OUT
EN5311QI
VS0
VS1
VS2
VFB
GND
VOLTAGE
SELECT
Figure 1. Typical application circuit.
Applications
•
•
•
•
•
•
•
Area constrained applications
Noise Sensitive Applications such as A/V
and RF
LDO replacement for improved thermals
Set top box/home gateway
Smart phones, PDAs
VoIP and Video phones
Personal Media Players
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EN5311QI
Pin
Description
other or to any external signal, voltage, or
ground. One or more of these pins may be
connected internally.
VSENSE
(Pin 15):
Sense pin for output
voltage regulation. Connect V
SENSE
to the
output voltage rail as close to the terminal of
the output filter capacitor as possible.
VFB
(Pin 16): Feedback pin for external divider
option. When using the external divider option
(VS0=VS1=VS2= high) connect this pin to the
center of the external divider. Set the divider
such that V
FB
= 0.603V.
Figure 2. Pin description, top view.
VIN
(Pin 1,2): Input voltage pin.
power to the IC.
Supplies
Input GND:
(Pin 3): Input power ground.
Connect this pin to the ground terminal of the
input
capacitor.
Refer
to
Layout
Recommendations for further details.
Output GND:
(Pin 4): Power ground. The
output filter capacitor should be connected
between this pin and V
OUT
. Refer to Layout
recommendations for further detail.
VOUT
(Pin 5,6,7): Regulated output voltage.
NC
(Pin 8,9,10,11,12,13,14): These pins
should not be electrically connected to each
VS0,VS1,VS2
(Pin 17,18,19): Output voltage
select. VS0=pin19, VS1=pin18, VS2=pin17.
Selects one of seven preset output voltages or
choose external divider by connecting pins to
logic high or low. Logic low is defined as V
LOW
≤
0.4V. Logic high is defined as V
HIGH
≥
1.4V.
Any level between these two values is
indeterminate.
ENABLE
(Pin 20): Output enable. Enable =
logic high, disable = logic low. Logic low is
defined as V
LOW
≤
0.2V. Logic high is defined
as V
HIGH
≥
1.4V. Any level between these two
values is indeterminate.
Bottom Thermal Pad:
Device thermal pad to
remove heat from package. Connect to PCB
surface ground pad and PCB internal ground
plane (see layout recommendations).
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EN5311QI
Functional Block Diagram
V
IN
UVLO
Thermal Limit
Current Limit
ENABLE
Soft Start
P-Drive
(-)
PWM
Comp
(+)
Logic
N-Drive
V
OUT
GND
Sawtooth
Generator
Compensation
Network
V
SENSE
(-)
Error
Amp
(+)
Switch
V
FB
DAC
VREF
Voltage
Select
Package Boundry
VS0 VS1 VS2
Figure 3. Functional Block Diagram.
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Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond
recommended operating conditions is not implied. Stress beyond absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods may affect device reliability.
PARAMETER
Input Supply Voltage
Voltages on: ENABLE, V
SENSE
, V
S0
-V
S2
Voltage on: V
FB
Storage Temperature Range
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
ESD Rating (based on Human Body Model)
SYMBOL
V
IN
MIN
-0.3
-0.3
-0.3
-65
MAX
7.0
V
IN
+ 0.3
2.7
150
260
2000
UNITS
V
V
V
°C
°C
V
T
STG
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
2.4
2.4
0.6
0
-40
-40
MAX
5.5
6.6
V
IN
-0.6
1000
+85
+125
UNITS
V
V
V
mA
°C
°C
Input Voltage Range (VID)
V
IN
1
Input Voltage Range (External Divider (VFB))
V
IN
Output Voltage Range
V
OUT
Output Current
I
OUT
Operating Ambient Temperature
T
A
Operating Junction Temperature
T
J
1. See Section “Application Information” for specific circuit requirements
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient (0 LFM)
Thermal Resistance: Junction to Case (0 LFM)
Thermal Shutdown
Thermal Shutdown Hysteresis
SYMBOL
θ
JA
θ
JC
T
J-TP
TYP
65
15
+150
15
UNITS
°C/W
°C/W
°C
°C
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Electrical Characteristics
NOTE: T
A
= 25°C unless otherwise noted. Typical values are at V
IN
= 3.6V, C
IN
= 4.7µF, C
OUT
=10µF.
NOTE: V
IN
must be greater than V
OUT
+ 0.6V.
PARAMETER
Operating Input Voltage
Under Voltage Lockout
UVLO Hysteresis
V
OUT
Initial Accuracy (VID)
V
OUT
Variation for all
Causes (VID)
Feedback Pin Voltage
Feedback Pin Voltage
Feedback Pin Input Current
Dynamic Voltage Slew
†
Rate
Output Current
Shut-Down Current
Quiescent Current
PFET OCP Threshold
VS0-VS1 Thresholds
VS0-VS2 Pin Input Current
Enable Voltage Threshold
SYMBOL
V
IN
V
UVLO
TEST CONDITIONS
Using VID
1
Using External Divider (VFB)
V
IN
going low to high
2.4V ≤ V
IN
≤ 5.5V, I
LOAD
= 100mA;
T
A
= 25C
2.4V ≤ V
IN
≤ 5.5V, I
LOAD
= 0 - 1A,
T
A
= -40°C to +85°C
2.4V ≤ V
IN
≤ 6.6V, I
LOAD
= 100mA
TA = 25C; VSO=VS1=VS2=1
2.4V ≤ V
IN
≤ 6.6V, I
LOAD
= 0 - 1A,
T
A
= -40°C to +85°C;
VSO=VS1=VS2=1
MIN
2.4
2.4
TYP
2.2
0.145
-2.0
-3.0
0.591
0.585
0.603
0.603
1
1.24
1000
1.65
0.75
800
1.4
0.0
1.4
1
0.0
1.4
2
4
340
270
.110
1.65
1.10
2
MAX
5.5
6.6
2.3
UNITS
V
V
V
V
V
OUT
V
OUT
V
FB
V
FB
I
FB
V
slew
I
OUT
I
SD
I
LIM
V
TH
I
VSX
+2.0
+3.0
0.615
0.621
%
%
V
V
nA
2.1
V/ms
mA
µA
µA
A
Enable = Low
No switching
2.4V
≤
V
IN
≤
6.6V,
0.6V
≤
V
OUT
≤
V
IN
– 0.6V
Pin = Low
Pin = High
Logic Low
Logic High
V
IN
= 3.6V
0.4
V
IN
nA
0.2
V
IN
V
µA
MHz
mΩ
mΩ
Ω
2.1
1.40
V/ms
ms
Enable Pin Input Current
I
EN
Operating Frequency
F
OSC
PFET On Resistance
R
DS(ON)
NFET On Resistance
R
DS(ON)
Typical inductor DCR
Soft-Start Operation
†
2
V
OUT
Soft Start Slew Rate
VID Mode
1.24
∆V
SS
2
Soft Start Rise Time
VFB mode
0.80
∆T
SS
1. See Section “Application Information” for specific circuit requirements
2. Measured from when V
IN
≥ V
UVLO
& ENABLE pin crosses its logic High threshold
† Parameter guaranteed by design.
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