Am29BDD160G
Data Sheet
For new designs, S29CD016G supersedes Am29BDD160G and is the factory-recommended migration
path for this device. Please refer to the S29CD016G datasheet for specifications and ordering infor-
mation.
The following document contains information on Spansion memory products. Although the doc-ument
is marked with the name of the company that originally developed the specification, Spansion will
continue to offer these products to existing customers.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when
appro-priate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
24960
Revision
D
Amendment
5
Issue Date
June 7, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29BDD160G
16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode,
Dual Boot, Simultaneous Read/Write Flash Memory
NOTE: For new designs, S29CD016G supersedes Am29BDD160G and is the factory-recommended migration path for this device. Please refer to the S29CD016G datasheet for specifica-
tions and ordering information.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank.
(–40°C to 85°C, 56 MHz and below only)
— Zero latency between read and write operations
— Two bank architecture: 75%/25%
User-Defined x16 or x32 Data Bus
Dual Boot Block
— Top and bottom boot in the same device
Flexible sector architecture
— Eight 8 Kbytes, thirty 64 Kbytes, and eight 8 Kbytes
sectors
Manufactured on 0.17 µm process technology
SecSi (Secured Silicon) Sector (256 Bytes)
— Current version of device has 64 Kbytes; future
versions will have 256 bytes
—
Factory locked and identifiable:
16 bytes for secure,
random factory Electronic Serial Number; remainder
may be customer data programmed by AMD
—
Customer lockable:
Can be read, programmed, or
erased just like other sectors. Once locked, data
cannot be changed
Programmable Burst interface
— Interface to any high performance processor
— Modes of Burst Read Operation:
Linear Burst: 4 double words (x32), 8 words (x16)
and double words (x32), and 32 words (x16) with
wrap around
Single power supply operation
— Optimized for 2.5 to 2.75 volt read, erase, and
program operations
Compatible with JEDEC standards (JC42.4)
— Pinout and software compatible with
single-power-supply flash standard
PERFORMANCE CHARACTERISTICS
High performance read access
— Initial/random access time as fast as 54 ns
— Burst access time as fast as 9 ns for ball grid array
package
Ultra low power consumption
— Burst Mode Read: 90 mA @ 66 MHz max
— Program/Erase: 50 mA max
— Standby mode: CMOS: 60 µA max
Minimum 1 million write cycles guaranteed per
sector
20 year data retention at 125°C
VersatileI/O
TM
control
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the V
IO
pin
— 1.65 V to 2.75 V compatible I/O signals
SOFTWARE FEATURES
Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector (requires only V
CC
levels)
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-definable 64-bit password
Supports Common Flash Interface (CFI)
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
HARDWARE FEATURES
Program Suspend/Resume & Erase
Suspend/Resume
— Suspends program or erase operations to allow
reading, programming, or erasing in same bank
Hardware Reset (RESET#), Ready/Busy# (RY/BY#),
and Write Protect (WP#) inputs
ACC input
— Accelerates programming time for higher throughput
during system production
Package options
— 80-pin PQFP
— 80-ball Fortified BGA
Publication#
24960
Rev:
D
Amendment:
5
Issue Date:
June 7, 2006
Refer to AMD’s Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am29BDD160
is a
16 Megabit, 2.5 Volt-only
sin-
gle power
supply burst
mode flash memory device.
The device can
be
configured for either 1,048,576
words
in
16-bit mode or 524,288 double words
in
32-bit
mode. The device can
also be
programmed
in
standard
EPROM programmers. The device offers
a
configurable
burst interface
to 16/32-bit microproces-
sors and
microcontrollers.
To eliminate
bus
contention, each device has
separate
chip enable (CE#), write enable (WE#)
and
output en-
able
(OE#) controls. Additional control
inputs are
re-
quired
for
synchronous burst
operations: Load Burst
Address Valid (ADV#),
and
Clock (CLK).
Each device requires only
a
single
2.5 or 2.6 Volt
power
supply
(2.5 V to 2.75 V) for
both
read
and
write
functions. A 12.0-volt V
PP
is
not required for program
or erase operations,
although an acceleration
pin
is
available if
faster programming performance
is
re-
quired.
The device
is
entirely command
set
compatible with
the
JEDEC
single-power-supply
Flash
standard.
The
software
command
set is
compatible with the
command
sets
of the 5 V Am29F
and 3
V Am29LV
Flash families. Commands
are
written to the command
register
using standard
microprocessor write timing.
Register contents
serve as inputs
to
an internal
state-machine
that controls the erase
and
program-
ming circuitry. Write cycles
also internally
latch
ad-
dresses
and
data needed for the programming
and
erase operations. Reading data out of the device
is
similar
to reading from other Flash or EPROM de-
vices.
The
Unlock Bypass
mode facilitates faster program-
ming times
by
requiring only two write cycles to pro-
gram data
instead
of four.
The
Simultaneous
Read/Write architecture
provides
simultaneous
operation
by
dividing the memory
space
into
two
banks.
The device can
begin
programming or
erasing
in
one
bank, and
then
simultaneously
read
from the other
bank,
with zero latency. This releases
the
system
from waiting for the completion of program
or erase operations.
See Simultaneous
Read/Write
Operations Overview
and
Restrictions on page 13.
The device provides
a
256-byte
SecSi™
(Secured
Silicon) Sector
with
an
one-time-programmable
(OTP) mechanism.
In
addition,
the device features
several
levels of
sector
protection, which can disable
both
the program
and
erase operations
in
certain
sectors
or
sector
groups:
Persistent
Sector
Protection
is a
command
sector
protection method that replaces the old 12 V con-
trolled protection method;
Password
Sector
Protec-
tion
is a
highly
sophisticated
protection method that
requires
a
password
before
changes to certain
sectors
or
sector
groups
are
permitted;
WP# Hardware Pro-
tection
prevents program or erase
in
the two outer-
most
8
Kbytes
sectors
of the larger
bank.
The device defaults to the Persistent
Sector
Protection
mode. The customer must then choose
if
the
Standard
or Password Protection method
is
most desirable. The
WP# Hardware Protection feature
is always available,
independent
of the other protection method chosen.
The
VersatileI/O™ (V
CCQ
)
feature
allows
the output
voltage generated on the device to
be
determined
based
on the V
IO
level. This feature
allows
this device
to operate
in
the 1.8 V I/O environment, driving
and
re-
ceiving
signals
to
and
from other 1.8 V devices on the
same bus.
In
addition, inputs and
I/Os that
are
driven
externally
are
capable of handling
3.6
V.
The host
system
can detect whether
a
program or
erase operation
is
complete
by
observing the RY/BY#
pin,
by
reading the DQ7 (Data# Polling), or DQ6 (tog-
gle)
status
bits.
After
a
program or erase cycle has
been
completed, the device
is
ready to read
array
data
or
accept another
command.
The
sector
erase architecture
allows
memory
sec-
tors to
be
erased
and
reprogrammed without
affecting
the data contents of other
sectors.
The device
is
fully
erased when
shipped
from the factory.
Hardware data protection
measures
include a
low
V
CC
detector that
automatically inhibits
write opera-
tions during power transitions. The
password and
software sector
protection
feature disables
both
program
and
erase operations
in any
combination of
sectors
of memory. This can
be achieved in-system at
V
CC
level.
The
Program/Erase
Suspend/Erase
Resume
fea-
ture enables the
user
to put erase on hold for
any
pe-
riod of time to read data from, or program data to,
any
sector
that
is
not
selected
for erasure. True
back-
ground erase can thus
be achieved.
The
hardware RESET# pin
terminates
any
operation
in
progress
and
resets the
internal state
machine to
reading
array
data.
The device offers two power-saving features. When
addresses
have
been stable
for
a specified amount
of
time, the device enters the
automatic
sleep
mode.
The
system
can
also
place the device
into
the
standby
mode.
Power consumption
is
greatly re-
duced
in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of
quality,
reliability
and
cost effective-
ness. The device electrically erases
all bits
within
a
sector simultaneously
via Fowler-Nordheim tunnelling.
The data
is
programmed
using
hot electron
injection.
2
Am29BDD160G
June 7, 2006
TABLE OF CONTENTS
Product
Selector
Guide
. . . . . . . . . . . . . . . . . . . . .
5
Block Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Block Diagram of
Simultaneous
Operation Circuit
. . . . . . . . . . . . .
6
Connection Diagram
. . . . . . . . . . . . . . . . . . . . . . . .
7
Special Package Handling Instructions .................................... 8
Pin Configuration
. . . . . . . . . . . . . . . . . . . . . . . . . .
9
Logic
Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
x16 Mode .................................................................................. 9
x32 Mode .................................................................................. 9
Ordering Information
. . . . . . . . . . . . . . . . . . . . . .
10
Device Bus Operations
. . . . . . . . . . . . . . . . . . . . .
11
Table 1. Device Bus Operation .......................................................12
Dynamic Protection Bit (DYB) ............................................. 25
Table 11. Sector Protection Schemes ............................................ 26
VersatileI/O™ (V
IO
) Control .................................................... 13
Requirements for Reading Array Data ................................... 13
Simultaneous Read/Write
Operations Overview and Restrictions ................................... 13
Overview ............................................................................. 13
Restrictions .......................................................................... 13
Table 2. Bank Assignment for Boot Bank
Sector Devices ................................................................................13
Persistent Sector Protection Mode Locking Bit ....................... 26
Password Protection Mode ..................................................... 26
Password and Password Mode Locking Bit ............................ 26
64-bit Password ................................................................... 27
Write Protect (WP#) ................................................................ 27
SecSi™ (Secured Silicon) Sector Protection .......................... 27
SecSi Sector Protection Bit ..................................................... 28
Persistent Protection Bit Lock ................................................. 28
Hardware Data Protection ...................................................... 28
Low V
CC
Write Inhibit ........................................................... 28
Write Pulse “Glitch” Protection ............................................ 28
Logical Inhibit ....................................................................... 28
Power-Up Write Inhibit ......................................................... 28
V
CC
and V
IO
Power-up And Power-down Sequencing ......... 28
Table 12. Sector Addresses for Top Boot Sector Devices ............. 29
Table 13. Sector Addresses for Bottom Boot Sector Devices ........ 30
Table 14. CFI Query Identification String ....................................... 31
Table 15. CFI System Interface String ........................................... 31
Table 16. CFI Device Geometry Definition ..................................... 32
Table 17. CFI Primary Vendor-Specific Extended Query ............... 32
Simultaneous Read/Write Operations With Zero Latency ...... 13
Table 3. Top Boot Bank Select .......................................................14
Table 4. Bottom Boot Bank Select ..................................................14
Writing Commands/Command Sequences ............................ 14
Accelerated Program and Erase Operations ....................... 14
Autoselect Functions ........................................................... 14
Automatic Sleep Mode (ASM) ................................................ 14
RESET#: Hardware Reset Pin ............................................... 15
Output Disable Mode .............................................................. 15
Autoselect Mode ..................................................................... 15
Table 5. Am29BDD160 Autoselect Codes (High Voltage Method) .16
Command Definitions
. . . . . . . . . . . . . . . . . . . . . 34
Reading Array Data in Non-burst Mode .................................. 34
Reading Array Data in Burst Mode ......................................... 34
Read/Reset Command ........................................................... 34
Autoselect Command ............................................................. 35
Program Command Sequence ............................................... 35
Accelerated Program Command ............................................ 35
Unlock Bypass Command Sequence ..................................... 35
Figure 4. Program Operation ......................................................... 36
Asynchronous Read Operation (Non-Burst) ........................... 16
Figure 1. Asynchronous Read Operation........................................ 16
Synchronous (Burst) Read Operation .................................... 17
Linear Burst Read Operations ................................................ 17
Table 6. 16-Bit and 32-Bit Linear and Burst Data Order .................17
CE# Control in Linear Mode ................................................ 18
ADV# Control In Linear Mode .............................................. 18
RESET# Control in Linear Mode ......................................... 18
OE# Control in Linear Mode ................................................ 18
IND/WAIT# Operation in Linear Mode ................................. 18
Table 7. Valid Configuration Register Bit Definition for IND/WAIT# 20
Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word
Burst Operation............................................................................... 20
Unlock Bypass Entry Command .......................................... 36
Unlock Bypass Program Command .................................... 36
Unlock Bypass Chip Erase Command ................................ 36
Unlock Bypass CFI Command ............................................ 36
Unlock Bypass Reset Command ......................................... 37
Chip Erase Command ............................................................ 37
Sector Erase Command ......................................................... 37
Figure 5. Erase Operation.............................................................. 38
Sector Erase and Program Suspend Command .................... 38
Sector Erase and Program Suspend Operation Mechanics ... 38
Table 18. Allowed Operations During Erase/Program Suspend ... 38
Burst Access Timing Control ............................................... 21
Initial Burst Access Delay Control ....................................... 21
Table 8. Burst Initial Access Delay ..................................................21
Figure 3. Initial Burst Delay Control ................................................ 21
Configuration Register ............................................................ 22
Table 9. Configuration Register Definitions .....................................22
Table 10. Configuration Register After Device Reset .....................24
Initial Access Delay Configuration .......................................... 24
Sector
Protection
. . . . . . . . . . . . . . . . . . . . . . . .
24
Persistent Sector Protection ................................................... 24
Persistent Protection Bit (PPB) ............................................ 25
Persistent Protection Bit Lock (PPB Lock) .......................... 25
Sector Erase and Program Resume Command ..................... 39
Configuration Register Read Command ................................. 39
Configuration Register Write Command ................................. 39
Common Flash Interface (CFI) Command .............................. 39
SecSi Sector Entry Command ................................................ 41
Password Program Command ................................................ 41
Password Verify Command .................................................... 41
Password Protection Mode Locking Bit Program Command .. 42
Persistent Sector Protection Mode Locking Bit Program Com-
mand ....................................................................................... 42
SecSi Sector Protection Bit Program Command .................... 42
PPB Lock Bit Set Command ................................................... 42
DYB Write Command ............................................................. 42
Password Unlock Command .................................................. 42
PPB Program Command ........................................................ 43
June 7, 2006
Am29BDD160G
3
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