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74F794SCX

Description
D Flip-Flop, F/FAST Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, TTL, PDSO20, 0.300 INCH, MS-013, SOIC-20
Categorylogic   
File Size50KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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74F794SCX Overview

D Flip-Flop, F/FAST Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, TTL, PDSO20, 0.300 INCH, MS-013, SOIC-20

74F794SCX Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP20,.4
Contacts20
Reach Compliance Codeunknown
Other featuresWITH READ-BACK
seriesF/FAST
JESD-30 codeR-PDSO-G20
JESD-609 codee0
length12.8 mm
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Sup90000000 Hz
MaximumI(ol)0.064 A
Number of digits8
Number of functions1
Number of terminals20
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP20,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)80 mA
Prop。Delay @ Nom-Sup8 ns
propagation delay (tpd)9 ns
Certification statusNot Qualified
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width7.5 mm
minfmax90 MHz
Base Number Matches1
74F794 8-Bit Register with Readback
March 1990
Revised August 1999
74F794
8-Bit Register with Readback
General Description
The 74F794 is an 8-bit register with readback capability
designed to store data as well as read the register informa-
tion back onto the data bus. The I/O bus (D bus) has 3-
STATE outputs. Current sinking capability is 64 mA on both
the D and Q busses.
Data is loaded into the registers on the LOW-to-HIGH tran-
sition of the clock (CP). The output enable (OE) is used to
enable data on D
0
–D
7
. When OE is LOW, the output of the
registers is enabled on D
0
–D
7
, enabling D as an output
bus. When OE is HIGH, D
0
–D
7
are inputs to the registers
configuring D as an input bus.
Features
s
3-STATE outputs on the I/O port
s
D and Q output sink capability of 64 mA
s
Functionally and pin equivalent to the 74LS794
Ordering Code:
Order Number
74F794SC
74F794PC
Package Number
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
© 1999 Fairchild Semiconductor Corporation
DS010652
www.fairchildsemi.com
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