Enable (CE), an active LOW Output Enable (OE), and
three-state drivers. These devices have an automatic pow-
er-down feature that reduces power consumption by more
than 65% when the devices are deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O
0
through I/O
3
) is then written into the location speci-
fied on the address pins (A
0
through A
17
).
Reading from the devices is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the four I/O pins.
The four input/output pins (I/O
0
through I/O
3
) are placed in a
high-impedance state when the devices are deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE and WE LOW).
The CY7C106B is available in a standard 400-mil-wide SOJ;
the CY7C1006B is available in a standard 300-mil-wide SOJ.
Functional Description
The CY7C106B and CY7C1006B are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits.
Easy memory expansion is provided by an active LOW Chip
Logic Block Diagram
Pin Configuration
SOJ
Top View
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
CE
OE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INPUT BUFFER
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
ROW DECODER
SENSE AMPS
I/O
3
I/O
2
I/O
1
I/O
0
V
CC
A
17
A
16
A
15
A
14
A
13
A
12
A
11
NC
I/O
3
I/O
2
I/O
1
I/O
0
WE
C106B–2
512 x 512 x 4
ARRAY
COLUMN
DECODER
POWER
DOWN
CE
WE
OE
C106B–1
Selection Guide
7C106B-12
7C1006B-12
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum Standby
Current (mA)
12
90
50
7C106B-15
7C1006B-15
15
80
30
7C106B-20
7C1006B-20
20
75
30
7C106B-25
7C1006B-25
25
70
30
7C106B-35
35
60
25
Cypress Semiconductor Corporation
Document #: 38-05037 Rev. **
A
0
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 24, 2001
CY7C106B
CY7C1006B
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage on V
CC
Relative to GND
[1]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................–0.5V to V
CC
+ 0.5V
Range
Commercial
Industrial
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Ambient
Temperature
[2]
0
°
C to +70
°
C
–45
°
C to +85
°
C
V
CC
5V
±
10%
Document #: 38-05037 Rev. **
Page 2 of 10
CY7C106B
CY7C1006B
Electrical Characteristics
Over the Operating Range
7C106B-12
7C1006B-12
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage Current
Output Short
Circuit Current
[3]
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage Current
Output Short
Circuit Current
[3]
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
,
V
IN
> V
IH
or V
IN
< V
IL
,
f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V
or V
IN
< 0.3V, f = 0
Com’l
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
,
V
IN
> V
IH
or V
IN
< V
IL
,
f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V
or V
IN
< 0.3V, f=0
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.3
–1
–5
Com’l
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.3
–1
–5
Min.
2.4
0.4
V
CC
+0.3
0.8
+1
+5
–300
90
2.2
–0.3
–1
–5
Max.
7C106B-15
7C1006B-15
Min.
2.4
0.4
V
CC
+0.3
0.8
+1
+5
–300
80
2.2
–0.3
–1
–5
Max.
7C106B-20
7C1006B-20
Min.
2.4
0.4
V
CC
+0.3
0.8
+1
+5
–300
75
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB1
50
30
30
mA
I
SB2
10
10
10
mA
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
2.4
0.4
V
CC
+
0.3
0.8
+1
+5
–300
70
2.4
0.4
2.2
–0.3
–1
–5
V
CC
+
0.3
0.8
+1
+5
–300
60
V
V
V
V
µA
µA
mA
mA
I
SB1
30
25
mA
I
SB2
10
10
mA
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “instant on” case temperature.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05037 Rev. **
Page 3 of 10
CY7C106B
CY7C1006B
Capacitance
[4]
Parameter
C
IN
: Addresses
C
IN
: Controls
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
7
10
10
Unit
pF
pF
pF
AC Test Loads and Waveforms
R1 480Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
255Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2 GND
255Ω
Rise Time < 1V/ns
R1 480Ω
3.0V
ALL INPUT PULSES
90%
10%
90%
10%
Fall Time < 1V/ns
(a)
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
167Ω
1.73V
(b)
C106B–3
C106B–4
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05037 Rev. **
Page 4 of 10
CY7C106B
CY7C1006B
Switching Characteristics
Over the Operating Range
[5]
7C106B-12 7C106B-15 7C106B-20 7C106B-25
7C1006B-12 7C1006B-15 7C1006B-20 7C1006B-25
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[7]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
12
10
10
0
0
10
7
0
2
6
0
12
15
12
12
0
0
12
8
0
3
7
3
6
0
15
20
15
15
0
0
15
10
0
3
8
0
6
3
7
0
20
25
20
20
0
0
20
15
0
3
10
3
12
6
0
7
3
8
0
25
35
25
25
0
0
25
20
0
3
10
12
12
3
15
7
0
8
3
10
0
35
15
15
3
20
8
0
10
3
10
20
20
3
25
10
0
10
25
25
3
35
10
35
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
7C106B-35
Min.
Max. Unit
WRITE CYCLE
[8, 9]
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30–pF load capacitance.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
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