Product Specification
PE4220
Product Description
The PE4220 UltraCMOS™ RF Switch is designed to cover a
broad range of applications from near DC to 2500 MHz. This
single-supply switch integrates on-board CMOS control logic
driven by a simple, single-pin CMOS or TTL compatible control
input. Using a nominal +3-volt power supply, a typical input 1
dB compression point of +22 dBm can be achieved. The
PE4220 also exhibits input-output isolation of better than 37 dB
at 1000 MHz and is offered in a small 8-lead MSOP package.
The PE4220 UltraCMOS™ RF Switch is manufactured in
Peregrine’s patented Ultra Thin Silicon (UTSi®) CMOS
process, offering the performance of GaAs with the economy
and integration of conventional CMOS.
Figure 1. Functional Diagram
RFC
SPDT UltraCMOS™ RF Switch
DC - 2500 MHz
Features
•
Single 3-volt power supply
•
Very low insertion loss: 0.25 dB at
1000 MHz
•
High isolation: 37 dB at 1.0 GHz
•
Typical input 1 dB compression point
of +22.5 dBm
•
Single-pin CMOS or TTL logic control
•
Packaged in a small 8-lead MSOP
Figure 2. Package Type
8-lead MSOP
RF1
RF2
CMOS
Control
Driver
CTRL
Table 1. Electrical Specifications @ +25 °C, V
DD
= 3 V
(Z
S
= Z
L
= 50
Ω)
Parameter
Operating Frequency
1
Insertion Loss
Isolation – RFC to RF1/RF2
Isolation – RF1 to RF2
Return Loss
‘ON’ Switching Time
‘OFF’ Switching Time
Video Feedthrough
2
Input 1 dB Compression
Input IP3
Notes:
2000 MHz
2000 MHz, 8 dBm
1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low
in a 50Ω test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
20
42
1000 MHz
1000 MHz
1000 MHz
1000 MHz
CTRL to 0.1 dB final value, 2 GHz
CTRL to 25 dB isolation, 2 GHz
34.5
34
17.5
Conditions
Minimum
DC
Typical
Maximum
2500
Units
MHz
dB
dB
dB
dB
ns
ns
mV
pp
dBm
dBm
0.25
37
35
19
200
90
5.0
22.5
43.5
0.35
Document No. 70-0028-09
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www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 7
PE4220
Product Specification
Figure 3. Pin Configuration (Top View)
V
DD
CTRL
1
2
8
7
RF1
Table 4. Absolute Maximum Ratings
Symbol
V
DD
Parameter/Conditions
Power supply voltage
Voltage on any input
Storage temperature range
Operating temperature
range
Input power (50Ω)
ESD voltage (Human Body
Model)
Min
-0.3
-0.3
-65
-40
Max
4.0
V
DD
+ 0.3
150
85
25
250
Units
V
V
°C
°C
dBm
V
GND
GND
V
I
T
ST
T
OP
4220
GND
RFC
3
4
6
5
RF2
P
IN
V
ESD
Table 2. Pin Descriptions
Pin
No.
1
Pin
Name
V
DD
Description
Nominal 3 V supply connection. A
bypass capacitor (100 pF) to the ground
plane should be placed as close as
possible to the pin
CMOS or TTL logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
2
CTRL
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. Control Logic Truth Table
Control Voltage
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
3
GND
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Common RF port for switch (Note 1)
RF2 port (Note 1)
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
RF1 port (Note 1)
4
5
6
RFC
RF2
GND
7
GND
8
RF1
Note 1: All RF pins must be DC blocked with an external
series capacitor or held at 0 V
DC
.
Signal Path
RFC to RF1
RFC to RF2
Table 3. DC Electrical Specifications
Parameter
V
DD
Power Supply Voltage
I
DD
Power Supply Current
(V
DD
= 3V, V
CNTL
= 3)
Control Voltage High
Control Voltage Low
0.7x V
DD
0.3x V
DD
Min
2.7
Typ
3.0
30
Max
3.3
40
Units
V
µA
V
V
Control Logic
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of V
DD
. For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the V
DD
pin when the
control logic input voltage level exceeds V
DD
.)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
Document No. 70-0028-09
│
UltraCMOS™ RFIC Solutions
PE4220
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4220 SPDT switch. The RF common port is
connected through a 50
Ω
transmission line to the
top left SMA connector, J1. Port 1 and Port 2 are
connected through 50
Ω
transmission lines to the top
two SMA connectors on the right side of the board,
J3 and J4. A through transmission line connects
SMA connectors J6 and J8. This transmission line
can be used to estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The bottom
layer provides ground for the RF transmission lines.
The transmission lines were designed using a
coplanar waveguide model with a trace width of
0.030”, trace gaps of 0.007”, dielectric thickness of
0.028”, metal thickness of 0.0014” and
ε
r
of 4.4. Note
that the predominate mode for these transmission
lines is coplanar waveguide with a ground plane.
J2 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left pin,
the second pin to the right (J2-3) is connected to the
device CTRL input. The fourth pin to the right (J2-7)
is connected to the device V
DD
input. A decoupling
capacitor (100 pF) is provided on both CTRL and
V
DD
traces. It is the responsibility of the customer to
determine proper supply decoupling for their design
application. Removing these components from the
evaluation board has not been shown to degrade RF
performance.
Figure 4. Evaluation Board Layout
Peregrine specification 101/0037
Figure 5. Evaluation Board Schematic
Peregrine specification 102/0035
Document No. 70-0028-09
│
www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 7
PE4220
Product Specification
Typical Performance Data @ -40 °C to 85 °C (Unless otherwise noted)
Figure 6. Insertion Loss – RFC to RF1
Figure 7. Input 1 dB Compression Point & IIP3
T = 25 °C
0
-0.25
25 C
-0.5
Insertion Loss (dB)
-0.75
-1
-1.25
IIP3 (dBm)
60
IIP3
60
-40 C
85 C
50
50
1 dB Compression Point (dBm)
40
40
30
30
20
20
1dB Compression
-1.5
-1.75
-2
0
500
1000
1500
2000
2500
10
10
0
500
1000
1500
2000
2500
0
3000
Frequency (MHz)
Frequency (MHz)
Figure 8. Insertion Loss – RFC to RF2
Figure 9. Isolation – RFC to RF1
T = 25 °C
0
-0.25
0
-20
-0.5
Insertion Loss (dB)
85 C
25 C
-1
-1.25
-1.5
-1.75
-2
0
500
1000
1500
2000
-0.75
-40 C
Isolation (dB)
-40
-60
-80
-100
2500
0
500
1000
1500
2000
2500
Frequency (MHz)
Frequency (MHz)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 7
Document No. 70-0028-09
│
UltraCMOS™ RFIC Solutions
PE4220
Product Specification
Typical Performance Data @ 25 °C
Figure 10. Isolation – RFC to RF2
Figure 11. Isolation – RF1/RF2 to RF2/RF1
0
0
-20
-20
RF2
Isolation (dB)
Isolation (dB)
-40
-40
-60
-60
RF1
-80
-80
-100
0
500
1000
1500
2000
2500
-100
0
500
1000
1500
2000
2500
Frequency (MHz)
Frequency (MHz)
Figure 12. Return Loss – RFC
Figure 13. Return Loss – RF1, RF2
0
0
RF2
-10
Return Loss (dB)
-10
-20
Return Loss (dB)
-20
RF1
-30
-30
-40
0
500
1000
1500
2000
2500
-40
0
500
1000
1500
2000
2500
Frequency (MHz)
Frequency (MHz)
Document No. 70-0028-09
│
www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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