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HD26LS32AP

Description
Quadruple Differential Line Receivers With 3 State Outputs
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size131KB,8 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Download Datasheet Parametric Compare View All

HD26LS32AP Overview

Quadruple Differential Line Receivers With 3 State Outputs

HD26LS32AP Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerRenesas Electronics Corporation
Parts packaging codeDIP
package instructionDIL-16
Contacts16
Reach Compliance Codeunknow
ECCN codeEAR99
Is SamacsysN
Input propertiesDIFFERENTIAL SCHMITT TRIGGER
Interface integrated circuit typeLINE RECEIVER
Interface standardsEIA-422-A; EIA-423
JESD-30 codeR-PDIP-T16
JESD-609 codee0
length19.2 mm
Number of functions4
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output low current0.008 A
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum receive delay35 ns
Number of receiver bits4
Maximum seat height5.06 mm
Maximum slew rate70 mA
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountNO
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
Base Number Matches1
HD26LS32A
Quadruple Differential Line Receivers With 3 State Outputs
REJ03D0296–0200Z
(Previous ADE-205-578 (Z))
Rev.2.00
Jul.16.2004
Description
The HD26LS32A features quadruple line receivers designed to meet the specs of EIA standard RS-422A and RS-423.
This device operates from a single 5 V power supply. The enable function is common to all four receivers and offers a
choice of active high or active low input. Fail safe design ensures that if the inputs are open, the outputs will always be
high.
Features
Ordering Information
Part Name
HD26LS32AP
Package Type
Package Code
P
Package
Abbreviation
Taping Abbreviation
(Quantity)
DILP-16 pin (JEITA) DP-16E, -16FV
Logic Diagram
1A
1B
2A
2B
3A
3B
4A
4B
Enable G
Enable G
1Y
2Y
3Y
4Y
Rev.2.00, Jul.16.2004, page 1 of 7

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HD26LS32AP HD26LS32A
Description Quadruple Differential Line Receivers With 3 State Outputs Quadruple Differential Line Receivers With 3 State Outputs
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