Si840x
B
IDIRECTIONAL
I
2
C I
SOLA TORS
D
IGITA L
C
HANNELS
Features
WITH
U
NIDIRECTIONAL
Applications
Isolated I
2
C, PMBus, SMBus
Power over Ethernet
Motor Control Systems
Description
The Si840x series of isolators are single-package galvanic isolation
solutions for I
2
C and SMBus serial port applications. These products are
based on Silicon Labs proprietary RF isolation technology and offer shorter
propagation delays, lower power consumption, smaller installed size, and
more stable operation with temperature and age versus opto couplers or
other digital isolators.
All devices in this family include hot-swap, bidirectional SDA and SCL
isolation channels with open-drain, 35 mA sink capability and operate to a
maximum frequency of 1.7 MHz. The 8-pin version (Si8400/01) supports
bidirectional SDA and SCL isolation; the Si8402 supports bidirectional SDA
and unidirectional SCL isolation, and the 16-pin version (Si8405) features
two unidirectional isolation channels to support additional system signals,
such as an interrupt or reset. All versions contain protection circuits to
guard against data errors if an unpowered device is inserted into a powered
system.
Small size, low installed cost, low power consumption, and short
propagation delays make the Si840x family the optimum solution for
isolating I
2
C and SMBus serial ports.
Safety Regulatory Approval
UL 1577 recognized
Up to 2500 V
RMS
for 1 minute
CSA component notice 5A approval
IEC 60950-1, 61010-1
(reinforced
insulation)
Rev. 1.6 10/13
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Hot-swap applications
Intelligent Power systems
Isolated SMPS systems with
PMBus interfaces
to 5.5 V
Supports
clocks up to 1.7 MHz
Wide temperature range
–40 to +125 °C max
Unidirectional isolation channels
support additional system signals
Transient immunity 25 kV/µs
(Si8405)
RoHS-compliant packages
Up to 2500 V
RMS
isolation
SOIC-8 narrow body
SOIC-16 narrow body
UL, CSA, VDE recognition
I
2
C
Independent, bidirectional SDA and
SCL isolation channels
Open drain outputs with 35 mA
sink current
60-year life at rated working voltage
High electromagnetic immunity
Wide operating supply voltage
3.0
Ordering Information:
See page 25.
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
Copyright © 2013 by Silicon Laboratories
Si840x
2
Si840x
Rev. 1.6
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Si840x
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.2. Under Voltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4. Input and Output Characteristics for Non-I2C Digital Channels . . . . . . . . . . . . . . . . 15
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. Typical Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1. I2C Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.2. I2C Isolator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3. I2C Isolator Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4. I2C Isolator Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1. Power Supply Bypass Capacitors (Revision A and Revision B) . . . . . . . . . . . . . . . . 22
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
9. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12. Top Marking: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
12.1. 8-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
12.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
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Rev. 1.6
3
Si840x
1. Electrical Specifications
Table 1. Absolute Maximum Ratings
1
Parameter
Storage Temperature
2
Ambient Temperature Under Bias
Supply Voltage (Revision A)
3
Supply Voltage (Revision B)
3
Input Voltage
Output Voltage
Symbol
T
STG
T
A
V
DD
V
DD
V
I
V
O
I
O
I
O
I
O
Min
–65
–40
–0.5
–0.5
–0.5
–0.5
—
—
—
Typ
—
—
—
—
—
—
Max
150
125
5.75
6.0
V
DD
+ 0.5
V
DD
+ 0.5
±10
±15
±75
260
3600
Unit
°C
°C
V
V
V
V
mA
mA
mA
°C
V
RMS
Output Current Drive (non-I
2
C channels)
Side A output current drive (I
2
C channels)
Side B output current drive (I
2
C channels)
Lead Solder Temperature (10 s)
Maximum Isolation Voltage (1 s)
Notes:
1.
Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2.
VDE certifies storage temperature from –40 to 150 °C.
3.
See "7.Ordering Guide" on page 25 for more information.
Table 2. Si840x Power Characteristics*
Parameter
Symbol
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C (See Figures 2 and 16 for test diagrams.)
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—
—
—
—
—
—
—
Test Condition
Min
Idda
Iddb
All channels = 0 dc
—
—
Idda
Iddb
All channels = 1 dc
—
—
Idda
Iddb
All channels = 1.7 MHz
—
—
Idda
Iddb
Idda
Iddb
Idda
Iddb
All non-I
2
C channels = 0
All I
2
C channels = 1
All non-I
2
C channels = 1
All I
2
C channels = 0
All non-I
2
C channels = 5 MHz
All I
2
C channels = 1.7 MHz
—
—
—
—
—
—
Rev. 1.6
Typ
Max
Unit
Si8400/01/02 Supply Current
AVDD current
BVDD current
4.2
3.9
2.3
1.9
6.3
5.9
3.5
2.9
4.8
4.4
mA
mA
mA
mA
mA
mA
AVDD current
BVDD current
AVDD current
BVDD current
Si8405 Supply Current
AVDD current
BVDD current
AVDD current
BVDD current
AVDD current
BVDD current
3.2
2.9
3.2
2.9
6.2
6.0
4.7
4.5
4.8
4.4
9.3
9.0
7.1
6.8
mA
mA
mA
mA
mA
mA
*Note:
All voltages are relative to respective ground.
4
Si840x
Table 3. Si8400/01/02/05 Electrical Characteristics for Bidirectional I
2
C Channels
1
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C unless otherwise noted.
Parameter
Logic Levels Side A
Logic Input Threshold
2
Logic Low Output Voltages
3
Input/Output Logic Low Level
Difference
4
Logic Levels Side B
Logic Low Input Voltage
Logic High Input Voltage
Logic Low Output Voltage
SCL and SDA Logic High
Leakage
Symbol
I
2
CV
T
(Side A)
I
2
CV
OL
(Side A)
I
2
CV (Side A)
Test Condition
Min
450
650
550
50
Typ
—
—
—
—
Max
780
910
825
—
Unit
mV
mV
mV
mV
ISDAA = ISCLA = 3.0 mA
ISDAA = ISCLA = 0.5 mA
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I
2
CV
IL
(Side B)
I
2
CV
IH
(Side B)
I
2
CV
OL
(Side B)
Isdaa, Isdab
Iscla, Isclb
CA
CB
ISCLB = 35 mA
—
2.0
—
—
SDAA, SCLA = VSSA
SDAB, SCLB = VSSB
—
—
Rev. 1.6
—
—
—
0.8
—
400
10
—
—
V
V
mV
µA
pF
pF
2.0
10
10
Pin capacitance SDAA, SCLA,
SDAB, SDBB
Notes:
1.
All voltages are relative to respective ground.
2.
V
IL
< 0.450 V, V
IH
> 0.780 V.
3.
Logic low output voltages are 910 mV max from –10 to 125 °C at 3.0 mA.
Logic low output voltages are 955 mV max from –40 to 125 °C at 3.0 mA.
Logic low output voltages are 825 mV max from –10 to 125 °C at 0.5 mA.
Logic low output voltages are 875 mV max from –40 to 125 °C at 0.5 mA.
See “AN375: Design Considerations for Isolating an I
2
C Bus or SMBus” for additional information.
4.
I
2
CV (Side A) = I
2
CV
OL
(Side A) – I
2
CV
T
(Side A). To ensure no latch-up on a given bus, I
2
CV (Side A) is the
minimum difference between the output logic low level of the driving device and the input logic threshold.
5.
Side A measured at 0.6 V.
5
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