7517 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0087-0101Z
Rev.1.01
Aug 02, 2004
q
Current integrator ......................................................... 1 channel
q
Over current detector ................................................... 1 channel
q
Watchdog timer ............................................................ 16-bit
✕
1
q
Clock generating circuit ..................................... Built-in 4 circuits
(built-in 4MHz on-chip oscillator and 32kHz RC oscillator, or con-
nect to external ceramic resonator or quartz-crystal oscillator)
q
Power source voltage
In high-speed mode .................................................. 3.0 to 3.6 V
(at 4 MHz oscillation frequency)
In middle-speed mode ............................................... 3.0 to 3.6 V
(at 8 MHz oscillation frequency)
In low-speed mode .................................................... 3.0 to 3.6 V
(at 32 kHz oscillation frequency)
q
Power dissipation
In high-speed mode ...................................................... 8.25 mW
(at 4 MHz oscillation frequency, at 3.3 V power source voltage)
In low-speed mode ........................................................... 660µW
(at 32 kHz oscillation frequency, at 3.3 V power source voltage)
q
Operating temperature range .................................... –20 to 85°C
DESCRIPTION
The 7517 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 7517 group is designed for battery-pack and includes serial
interface functions, 8-bit timer, A/D converter, current integrator
and I
2
C-BUS interface.
FEATURES
qBasic
machine-language instructions ...................................... 71
qMinimum
instruction execution time .................................. 1.0
µs
(at 4 MHz oscillation frequency)
qMemory
size
Flash memory ............................................................... 32 kbytes
RAM ................................................................................ 1 kbytes
qProgrammable
input/output ports ............................................ 36
qInterrupts
................................................. 19 sources, 16 vectors
qTimers
............................................................................. 8-bit
✕
4
qSerial
I/O1 ................... 8-bit
✕
1 (UART or Clock-synchronized)
qSerial
I/O2 ................................... 8-bit
✕
1(Clock-synchronized)
qMulti-master
I
2
C-BUS interface (option) ...................... 1 channel
qPWM
............................................................................... 8-bit
✕
1
qA/D
converter ............................................. 10-bit
✕
10 channels
APPLICATION
Battery-Pack, etc.
PIN CONFIGURATION (TOP VIEW)
P0
1
/S
OUT2
P1
0
/(LED
0
)
26
P0
3
/S
RDY2
P0
2
/S
CLK2
P3
5
/AN
5
P0
4
/AN
6
P0
6
/AN
8
P0
0
/S
IN2
P0
7
/AN
9
36
34
32
31
33
29
35
P3
3
/AN
3
P3
2
/AN
2
P3
1
/AN
1
P3
0
/AN
0
ADV
SS
ADV
REF
V
CC
AV
CC
AV
SS
ISENS0
ISENS1
DFETCNT/P4
5
37
38
39
40
41
42
43
44
45
46
47
48
30
28
27
25
P1
1
/(LED
1
)
P3
4
/AN
4
P0
5
/AN
7
24
23
22
21
20
P1
2
/(LED
2
)
P1
3
/(LED
3
)
P1
4
/(LED
4
)
P1
5
/(LED
5
)
P1
6
/(LED
6
)
P1
7
/(LED
7
)
V
SS
X
OUT
X
IN
RESET
P2
0
/X
COUT
P2
1
/X
CIN
M37517F8HP
19
18
17
16
15
14
13
10
11
P4
4
/INT
3
/PWM
P2
7
/CNTR
0
/S
RDY1
P4
3
/INT
2
/S
CMP2
P2
4
/SDA
2
/R
X
D
P4
0
/CNTR
1
P2
5
/SCL
2
/T
X
D
P2
2
/SDA
1
P2
6
/S
CLK
P2
3
/SCL
1
P4
2
/INT
1
Package type : 48P6Q-A
Fig. 1 M37517F8HP pin configuration
Rev.1.01
Aug 02, 2004
page 1 of 96
P4
1
/INT
0
CNV
SS
12
1
7
3
2
4
5
6
8
9
Rev.1.01
V
SS
V
CC
43
15
12
18
7517 Group
FUNCTIONAL BLOCK DIAGRAM
Main-clock
input
X
IN
Reset input
RESET
CNV
SS
Main-clock
output
X
OUT
FUNCTIONAL BLOCK
Fig. 2 Functional block diagram
Aug 02, 2004
C P U
16
17
Clock generating circuit
X
Prescaler 12 (8)
page 2 of 96
RAM
ROM
Y
Prescaler X (8)
A
Timer 1 (8)
Timer 2 (8)
Timer X (8)
Timer Y (8)
X
CIN
sub-clock input
X
COUT
sub-clock output
S
CNTR
0
Prescaler Y (8)
PC
H
PC
L
PS
CNTR
1
Watchdog timer
Reset
0
Over current
detector
PWM (8)
SI/O1(8)
Current
integrator
I
2
C
(8)
10-bit
A/D
converter
SI/O2(8)
X
CIN
X
COUT
INT
0
- INT
3
P4(6)
P3(6)
P2(8)
P1(8)
P0(8)
ISENS1
48 1 2 3 4 5
AVcc
35 36 37 38 39 40
6 7 8 9 10 11 13 14
19 20 21 22 23 24 25 26
27 28 29 30 31 32 33 34
47 46 45 44
41 42
ISENS0 AVss
ADV
SS
ADV
REF
I/O port P 4
I/O port P 3
I/O port P 2
I/O port P 1
I/O port P 0
7517 Group
PIN DESCRIPTION
Table 1 Pin description
Pin
V
CC
, V
SS
AV
CC
AV
SS
ADV
SS
AD
VREF
CNV
SS
RESET
X
IN
X
OUT
Name
Power source
Analog power
source
Analog reference
voltage
CNV
SS
input
Reset input
Clock input
Clock output
Functions
•Apply voltage of 3.3V to Vcc, and 0 V to Vss.
•Apply voltage of 3.3V to AVcc, and 0 V to AVss and ADVss.
Function except a port function
•Reference voltage input pin for A/D converter.
•This pin controls the operation mode of the chip.
•Normally connected to V
SS
.
•Reset input pin for active “L”.
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the X
IN
and X
OUT
pins to set
the oscillation frequency.
•When an on-chip oscillator is used, leave the X
IN
pin and X
OUT
pin open.
•When an external clock is used, connect the clock source to the X
IN
pin and leave the X
OUT
pin open.
• Serial I/O2 function pin
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•P2
2
to P2
5
can be switched between CMOS compat-
ible input level or SMBUS input level in the I
2
C-BUS
interface function.
•P2
0
, P2
1
, P2
4
to P2
7
: CMOS3-state output structure.
•P2
4
, P2
5
: N-channel open-drain structure in the I
2
C-
BUS interface function.
•P2
2
, P2
3
: N-channel open-drain structure.
• I
2
C-BUS interface function pin/
Serial I/O1 function pin
• Serial I/O1 function pin
• Serial I/O1 function pin/
Timer X function pin
• A/D converter input pin
P0
0
/S
IN2
P0
1
/S
OUT2
P0
2
/S
CLK2
P0
3
/S
RDY2
P0
4
/AN
8
–P0
7
/AN
11
P1
0
–P1
7
P2
0
/X
COUT
P2
1
/X
CIN
P2
2
/SDA
1
P2
3
/SCL
1
P2
4
/SDA
2
/RxD
P2
5
/SCL
2
/TxD
P2
6
/S
CLK
P2
7
/CNTR
0
/
S
RDY1
I/O port P0
I/O port P1
I/O port P2
•P1
0
to P1
7
(8 bits) are enabled to output large current for LED drive.
• Sub-clock generating circuit I/O
pins (connect a resonator)
• I
2
C-BUS interface function pin
P3
0
/AN
0
–
P3
5
/AN
5
I/O port P3
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
• A/D converter input pin
P4
0
/CNTR
1
P4
1
/INT
0
P4
2
/INT
1
P4
3
/INT
2
/S
CMP2
P4
4
/INT
3
/PWM
P4
5
/DFETCNT
ISENS0
ISENS1
I/O port P4
•6-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
• Timer Y function pin
• Interrupt input pin
• Interrupt input pin/S
CMP2
output pin
• Interrupt input pin/PWM output pin
• Over current detector function pin
Analog input
•Input pins for the current integrator and the over current detector. Connect these pins at both
ends of a detection resistor, and connect ISENS0 to GND.
Rev.1.01
Aug 02, 2004
page 3 of 96
7517 Group
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 7517 group uses the standard 740 Family instruction set. Re-
fer to the table of 740 Family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[CPU Mode Register (CPUM)] 003B
16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B
16
.
b7
b0
CPU mode register
(
CPUM : address
003B
16
)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1:
1 0:
Not available
1 1:
Stack page selection bit
0 : 0 page
1 : 1 page
Clock source switch bit
0 : On-chip oscillation function
1 : X
CIN
–X
COUT
oscillation function
Port X
C
switch bit
0 : I/O port function (stop oscillating)
1 : X
CIN
–X
COUT
oscillation function
Main clock (X
IN
–X
OUT
) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 :
φ
= f(X
IN
)/2 (high-speed mode)
0 1 :
φ
= f(X
IN
)/8 (middle-speed mode)
1 0 :
φ
= f(X
CIN
)/2 (low-speed mode)
1 1 : Not available
Note : All bits in this register are protected by protect mode.
Fig. 3 Structure of CPU mode register
Rev.1.01
Aug 02, 2004
page 4 of 96
7517 Group
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Special Page
Access to this area with only 2 bytes is possible in the special
page addressing mode.
Flash Memory
The first 128 bytes and the last 2 bytes of flash memory are re-
served for device testing and the rest is user area for storing
programs.
0000
16
0040
16
RAM
1024 bytes
0100
16
SFR area
Zero page
0440
16
0FFD
16
0FFF
16
Flash memory
32 kbytes
8000
16
Not used
SFR area
Not used
Reserved memory area
(
128 bytes
)
8080
16
FF00
16
FFD4
16
FFDC
16
Interrupt vector area
FFFE
16
FFFF
16
Reserved memory area
Flash memory ID code
Special page
Fig. 4 Memory map diagram
Rev.1.01
Aug 02, 2004
page 5 of 96
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