Chapter 4. Serial Configuration
Devices (EPCS1, EPCS4,
EPCS16 & EPCS64) Data Sheet
C51014-2.0
Features
The serial configuration devices provide the following features:
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■
■
■
■
■
■
■
■
■
■
■
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1-, 4-, 16-, and 64-Mbit flash memory devices that serially configure
Stratix
®
II FPGAs and the Cyclone™ series FPGAs using the active
serial (AS) configuration scheme
Easy-to-use four-pin interface
Low cost, low pin count and non-volatile memory
Low current during configuration and near-zero standby mode
current
3.3-V operation
Available in 8-pin and 16-pin small outline integrated circuit (SOIC)
package
Enables the Nios
®
processor to access unused flash memory through
AS memory interface
Re-programmable memory with more than 100,000 erase/program
cycles
Write protection support for memory sectors using status register
bits
In-system programming support with SRunner software driver
Programming support with USB Blaster™ or ByteBlaster™ II
download cables
Additional programming support with the Altera
®
Programming
Unit (APU) and programming hardware from BP Microsystems,
System General, and other vendors
Software design support with the Altera Quartus
®
II development
system for Windows-based PCs as well as Sun SPARC station and
HP 9000 Series 700/800
Delivered with the memory array erased (all the bits set to
1)
Whenever the term “serial configuration device(s)” is used in
this document, it refers to Altera EPCS1, EPCS4, EPCS16, and
EPCS64 devices.
1
Functional
Description
With SRAM-based devices such as Stratix II FPGAs and the Cyclone
series FPGAs, configuration data must be reloaded each time the device
powers up, the system initializes, or when new configuration data is
needed. Serial configuration devices are flash memory devices with a
Altera Corporation
July 2004
Core Version a.b.c variable
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Preliminary
Functional Description
serial interface that can store configuration data for a Stratix II FPGA or a
Cyclone series device and reload the data to the device upon power-up or
reconfiguration.
Table 4–1
lists the serial configuration devices.
Table 4–1. Serial Configuration Devices (3.3-V Operation)
Device
EPCS1
EPCS4
EPCS16
EPCS64
Note to
Table 4–1:
(1)
This information is preliminary.
Memory Size (Bits)
1,048,576
4,194,304
16,777,216
(1)
67,108,864
(1)
You can vertically migrate from the EPCS1 to the EPCS4 device since they
are offered in the same device package. Similarly, you can vertically
migrate from the EPCS16 to the EPCS64 device.
Table 4–2
lists the serial configuration device used with each Stratix II
FPGA and the configuration file size. Stratix II devices can only be used
with EPCS16 or EPCS64 devices.
Table 4–2. Serial Configuration Device Support for Stratix II Devices
Stratix II Device
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
Notes to
Table 4–2:
(1)
(2)
These are preliminary, uncompressed file sizes.
This is with the Stratix II compression feature enabled.
Raw Binary File Size
(Bits)
(1)
5,000,000
10,100,000
17,100,000
27,500,000
39,600,000
52,400,000
Serial Configuration Device
EPC16
v
v
v
(2)
EPCS64
v
v
v
v
v
v
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Altera Corporation
July 2004
Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
Table 4–3
lists the serial configuration device used with each Cyclone II
FPGA and the configuration file size. Cyclone II devices can be used with
all serial configuration devices.
Table 4–3. Serial Configuration Device for Cyclone II Devices
Cyclone II Device
EP2C5
EP2C8
EP2C20
EP2C35
EP2C50
EP2C70
Notes to
Table 4–3:
(1)
(2)
These are preliminary, uncompressed file sizes.
This is with the Cyclone II compression feature enabled.
Raw Binary File
Size (Bits)
(1)
1,223,980
1,983,792
3,930,986
7,071,234
9,122,148
10,249,694
Serial Configuration Device
EPCS1
v
(2)
EPCS4
v
v
v
EPCS16 EPCS64
v
v
v
v
v
v
v
v
v
v
v
v
Table 4–4
lists the serial configuration device used with each Cyclone
FPGA and the configuration file size. Cyclone devices can only be used
with EPCS1, EPCS4, or EPCS16 devices.
Table 4–4. Serial Configuration Device Support for Cyclone Devices
Cyclone Device
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
Notes to
Table 4–4:
(1)
(2)
These are preliminary, uncompressed file sizes.
This is with the Cyclone compression feature enabled.
Raw Binary File
Size (Bits)
(1)
627,376
925,000
1,167,216
2,326,528
3,559,608
Serial Configuration Device
EPCS1
v
v
v
(2)
EPCS4
v
v
v
v
v
EPCS16
v
v
v
v
v
With the new data-decompression feature in the Stratix II and Cyclone
FPGA families, designers can use smaller serial configuration devices to
configure larger FPGAs.
Altera Corporation
July 2004
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Configuration Handbook, Volume 2
Functional Description
1
Serial configuration devices cannot be cascaded.
f
f
See
Configuring Stratix II Devices
in the Configuration Handbook for
more information regarding the Stratix II FPGA decompression feature.
See
Configuring Cyclone II Devices
in the Configuration Handbook for
more information regarding the Cyclone II FPGA decompression
feature.
See
Configuring Cyclone FPGAs
in the Configuration Handbook for more
information regarding the Cyclone FPGA decompression feature.
The serial configuration devices are designed to configure Stratix II
FPGAs and the Cyclone series FPGAs and cannot configure other existing
Altera device families.
Figure 4–1
shows the serial configuration device block diagram.
f
Figure 4–1. Serial Configuration Device Block Diagram
Serial Configuration Device
nCS
DCLK
Control
Logic
DATA
I/O Shift
Register
ASDI
Address Counter
Data Buffer
Status Register
Decode Logic
Memory
Array
4–4
Configuration Handbook, Volume 2
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Altera Corporation
July 2004
Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
Accessing Memory in Serial Configuration Devices
You can access the unused memory locations of the serial configuration
device to store or retrieve data through the Nios processor and SOPC
Builder. SOPC Builder is an Altera tool for creating bus-based (especially
microprocessor-based) systems in Altera devices. SOPC Builder
assembles library components like processors and memories into custom
microprocessor systems.
SOPC Builder includes the active serial memory interface (ASMI)
peripheral, an interface core specifically designed to work with the serial
configuration device. Using this core, you can create a system with a Nios
embedded processor that allows software access to any memory location
within the serial configuration device.
f
For more information on accessing memory within the serial
configuration device, see the
Active Serial Memory Interface Data Sheet.
Stratix II FPGAs and the Cyclone series FPGAs can be configured with a
serial configuration device through the AS configuration mode.
1
This section is only relevant for FPGAs that support the Active
Serial (AS) configuration scheme. Only Stratix II FPGAs and the
Cyclone series FPGAs support the AS configuration scheme.
Active Serial
FPGA
Configuration
There are four signals on the serial configuration device that interface
directly with the FPGA’s control signals. The serial configuration device
signals
DATA, DCLK, ASDI,
and
nCS
interface with
DATA0, DCLK, ASDO,
and
nCSO
control signals on the FPGA, respectively.
Figure 4–2
shows a
serial configuration device programmed via a download cable which
configures an FPGA in AS mode.
Figure 4–3
shows a serial configuration
device programmed using the APU or a third-party programmer
configuring an FPGA in AS configuration mode.
Altera Corporation
July 2004
Core Version a.b.c variable
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Configuration Handbook, Volume 2
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