FPGA - Field Programmable Gate Array MX
| Parameter Name | Attribute value |
| Is it Rohs certified? | conform to |
| Maker | Microsemi |
| package instruction | QCCJ, |
| Reach Compliance Code | compliant |
| ECCN code | 3A001.A.2.C |
| Other features | ALSO OPERATES AT 5V SUPPLY |
| maximum clock frequency | 92 MHz |
| Combined latency of CLB-Max | 2.3 ns |
| JESD-30 code | S-PQCC-J68 |
| JESD-609 code | e3 |
| length | 24.2316 mm |
| Humidity sensitivity level | 3 |
| Configurable number of logic blocks | 295 |
| Equivalent number of gates | 3000 |
| Number of terminals | 68 |
| Maximum operating temperature | 125 °C |
| Minimum operating temperature | -55 °C |
| organize | 295 CLBS, 3000 GATES |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | QCCJ |
| Package shape | SQUARE |
| Package form | CHIP CARRIER |
| Peak Reflow Temperature (Celsius) | 245 |
| Programmable logic type | FIELD PROGRAMMABLE GATE ARRAY |
| Certification status | Not Qualified |
| Maximum seat height | 4.572 mm |
| Maximum supply voltage | 3.6 V |
| Minimum supply voltage | 3 V |
| Nominal supply voltage | 3.3 V |
| surface mount | YES |
| technology | CMOS |
| Temperature level | MILITARY |
| Terminal surface | Matte Tin (Sn) |
| Terminal form | J BEND |
| Terminal pitch | 1.27 mm |
| Terminal location | QUAD |
| Maximum time at peak reflow temperature | 40 |
| width | 24.2316 mm |
| Base Number Matches | 1 |
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