AT45DB321E-MHF-T datasheet, PDF

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AT45DB321E-MHF-T: DescriptionNOR Flash 32M, 85MHz 2.3-3.6V DataFlash; Categorystorage storage; File Size2MB，70 Pages; ManufacturerAdesto Technologies; Environmental Compliance

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AT45DB321E-MHF-T Overview

NOR Flash 32M, 85MHz 2.3-3.6V DataFlash

AT45DB321E-MHF-T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	SON
package instruction	HVSON, SOLCC8,.25
Contacts	8
Reach Compliance Code	compliant
Factory Lead Time	10 weeks
Maximum clock frequency (fCLK)	70 MHz
Data retention time - minimum	20
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PDSO-N8
JESD-609 code	e4
length	6 mm
memory density	33554432 bit
Memory IC Type	FLASH
memory width	1
Number of functions	1
Number of terminals	8
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	32MX1
Package body material	PLASTIC/EPOXY
encapsulated code	HVSON
Encapsulate equivalent code	SOLCC8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	260
power supply	2.5/3.3 V
Programming voltage	2.7 V
Certification status	Not Qualified
Maximum seat height	0.6 mm
Serial bus type	SPI
Maximum standby current	0.000001 A
Maximum slew rate	0.022 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
type	NOR TYPE
width	5 mm
write protect	HARDWARE/SOFTWARE
Base Number Matches	1

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AT45DB321E

32-Mbit DataFlash (with Extra 1-Mbits), 2.3V Minimum

SPI Serial Flash Memory

Features



Single 2.3V - 3.6V supply



Serial Peripheral Interface (SPI) compatible

Supports SPI modes 0 and 3

Supports RapidS

™

operation



Continuous read capability through entire array



Up to 85MHz



Low-power read option up to 15MHz



Clock-to-output time (t

) of 6ns maximum



User configurable page size



512 bytes per page



528 bytes per page (default)



Page size can be factory pre-configured for 512 bytes



Two fully independent SRAM data buffers (512/528 bytes)



Flexible programming options

Byte/Page Program (1 to 512/528 bytes) directly into main memory

Buffer Write

Buffer to Main Memory Page Program



Flexible erase options



Page Erase (512/528 bytes)



Block Erase (4KB)



Sector Erase (64KB)



Chip Erase (32-Mbits)



Program and Erase Suspend/Resume



Advanced hardware and software data protection features

Individual sector protection

Individual sector lockdown to make any sector permanently read-only



128-byte, One-Time Programmable (OTP) Security Register



64 bytes factory programmed with a unique identifier



64 bytes user programmable



Hardware and software controlled reset options



JEDEC Standard Manufacturer and Device ID Read



Low-power dissipation

400nA Ultra-Deep Power-Down current (typical)

3µA Deep Power-Down current (typical)

25µA Standby current (typical)

7mA Active Read current (typical)



Endurance: 100,000 program/erase cycles per page minimum



Data retention: 20 years



Green (Pb/Halide-free/RoHS compliant) packaging options



8-lead SOIC (0.208" wide)

8-pad Ultra-thin DFN (5 x 6 x 0.6mm)

9-ball Ultra-thin UBGA (6 x 6 x 0.6mm)

Die in Wafer Form

8784K–DFLASH–9/2017

Table 1-1.

Pin Configurations

Asserted

State

Symbol

Name and Function

Chip Select:

Asserting the CS pin selects the device. When the CS pin is deasserted, the

device will be deselected and normally be placed in the standby mode (not Deep Power-Down

mode) and the output pin (SO) will be in a high-impedance state. When the device is

deselected, data will not be accepted on the input pin (SI).

A high-to-low transition on the CS pin is required to start an operation and a low-to-high

transition is required to end an operation. When ending an internally self-timed operation such

as a program or erase cycle, the device will not enter the standby mode until the completion of

the operation.

Serial Clock:

This pin is used to provide a clock to the device and is used to control the flow of

data to and from the device. Command, address, and input data present on the SI pin is

always latched on the rising edge of SCK, while output data on the SO pin is always clocked

out on the falling edge of SCK.

Serial Input:

The SI pin is used to shift data into the device. The SI pin is used for all data input

including command and address sequences. Data on the SI pin is always latched on the rising

edge of SCK. Data present on the SI pin will be ignored whenever the device is deselected (CS

is deasserted).

Serial Output:

The SO pin is used to shift data out from the device. Data on the SO pin is

always clocked out on the falling edge of SCK. The SO pin will be in a high-impedance state

whenever the device is deselected (CS is deasserted).

Write Protect:

When the WP pin is asserted, all sectors specified for protection by the Sector

Protection Register will be protected against program and erase operations regardless of

whether the Enable Sector Protection command has been issued or not. The WP pin functions

independently of the software controlled protection method. After the WP pin goes low, the

contents of the Sector Protection Register cannot be modified.

Type

Low

Input

SCK

—

Input

—

Input

—

Output

If a program or erase command is issued to the device while the WP pin is asserted, the device

will simply ignore the command and perform no operation. The device will return to the idle

state once the CS pin has been deasserted. The Enable Sector Protection command and the

Sector Lockdown command, however, will be recognized by the device when the WP pin is

asserted.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection

will not be used. However, it is recommended that the WP pin also be externally connected to

whenever possible.

Reset:

A low state on the reset pin (RESET) will terminate the operation in progress and reset

the internal state machine to an idle state. The device will remain in the reset condition as long

as a low level is present on the RESET pin. Normal operation can resume once the RESET pin

is brought back to a high level.

The device incorporates an internal power-on reset circuit, so there are no restrictions on the

RESET pin during power-on sequences. If this pin and feature is not utilized, then it is

recommended that the RESET pin be driven high externally.

Low

Input

RESET

Low

Input

GND

Device Power Supply:

The V

pin is used to supply the source voltage to the device.

Operations at invalid V

voltages may produce spurious results and should not be attempted.

Ground:

The ground reference for the power supply. GND should be connected to the system

ground.

—

Power

Ground

AT45DB321E

8784K–DFLASH–9/2017

AT45DB321E-MHF-T Related Products

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Description	NOR Flash 32M, 85MHz 2.3-3.6V DataFlash	NOR Flash 32M, 85MHz 2.3-3.6V DataFlash	NOR Flash 32Mb, 2.3V, 85Mhz Serial Flash	NOR Flash 32M, 85MHz 2.3-3.6V DataFlash	NOR Flash 32M, 85MHz 2.3-3.6V DataFlash	NOR Flash 8-VDFN (6x8), IND TEMP, QUAD, 2.3V, T&R, BINARY MODE, QE BIT ENABLED	NOR Flash 32Mb, 2.3V, 85Mhz Serial Flash	NOR Flash 32M, 85MHz 2.3-3.6V DataFlash
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	-	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	-	conform to	conform to
Parts packaging code	SON	SOIC	SOIC	SON	BGA	-	SOIC	DFN
package instruction	HVSON, SOLCC8,.25	SOP,	SOP,	HVSON, SOLCC8,.25	VBGA,	-	SOP,	HVSON,
Contacts	8	8	8	8	9	-	8	8
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	-	compliant	compliant
Factory Lead Time	10 weeks	10 weeks	10 weeks	10 weeks	-	-	10 weeks	13 weeks
Maximum clock frequency (fCLK)	70 MHz	85 MHz	85 MHz	70 MHz	85 MHz	-	85 MHz	85 MHz
JESD-30 code	R-PDSO-N8	R-PDSO-G8	R-PDSO-G8	R-PDSO-N8	S-PBGA-B9	-	R-PDSO-G8	R-PDSO-N8
JESD-609 code	e4	e4	e4	e4	e1	-	e4	e4
length	6 mm	5.29 mm	5.29 mm	6 mm	6 mm	-	5.29 mm	8 mm
memory density	33554432 bit	33554432 bit	33554432 bit	33554432 bit	33554432 bit	-	33554432 bit	33554432 bit
Memory IC Type	FLASH	FLASH	FLASH	FLASH	FLASH	-	FLASH	FLASH
memory width	1	1	1	1	1	-	1	1
Number of functions	1	1	1	1	1	-	1	1
Number of terminals	8	8	8	8	9	-	8	8
word count	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	-	33554432 words	33554432 words
character code	32000000	32000000	32000000	32000000	32000000	-	32000000	32000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	-	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-	-40 °C	-40 °C
organize	32MX1	32MX1	32MX1	32MX1	32MX1	-	32MX1	32MX1
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HVSON	SOP	SOP	HVSON	VBGA	-	SOP	HVSON
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	SQUARE	-	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE	GRID ARRAY, VERY THIN PROFILE	-	SMALL OUTLINE	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
Parallel/Serial	SERIAL	SERIAL	SERIAL	SERIAL	SERIAL	-	SERIAL	SERIAL
Peak Reflow Temperature (Celsius)	260	260	260	260	260	-	260	260
Programming voltage	2.7 V	3 V	3 V	2.7 V	3 V	-	3 V	3 V
Maximum seat height	0.6 mm	2.16 mm	2.16 mm	0.6 mm	0.6 mm	-	2.16 mm	1 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	-	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	-	2.3 V	2.3 V
Nominal supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	-	3 V	3 V
surface mount	YES	YES	YES	YES	YES	-	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	-	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Tin/Silver/Copper (Sn/Ag/Cu)	-	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	NO LEAD	GULL WING	GULL WING	NO LEAD	BALL	-	GULL WING	NO LEAD
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1 mm	-	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	BOTTOM	-	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
width	5 mm	5.24 mm	5.24 mm	5 mm	6 mm	-	5.24 mm	6 mm
Maker	-	Adesto Technologies	Adesto Technologies	Adesto Technologies	Adesto Technologies	-	Adesto Technologies	Adesto Technologies
Humidity sensitivity level	-	1	1	1	3	-	1	1

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