CY2X014
CY2X0147
Low-Jitter LVPECL Crystal Oscillator
Low-Jitter LVPECL Crystal Oscillator
Features
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Functional Description
The CY2X014/CY2X0147 device is a high-performance and
high-frequency XO. The device uses a Cypress proprietary
low-noise PLL to synthesize the frequency from an integrated
crystal.
The CY2X014/CY2X0147 device is available as a
factory-configured device or as a field-programmable device.
Factory-configured devices are configured for general use or
they can be customer-specific. The same CY2X014/CY2X0147
can be configured as four different device types as mentioned in
the
Logic Block Diagram.
For a complete list of related documentation,
click here.
Low-jitter crystal oscillator (XO)
Less than 1 ps typical root mean square (RMS) phase jitter
Low-voltage positive emitter coupled logic (LVPECL) output
Output frequency from 50 MHz to 690 MHz
Factory-configured or field-programmable
Integrated phase-locked loop (PLL)
Can be configured as four different devices
Supply voltage: 3.3 V or 2.5 V
Pb-free chip carrier (LCC): 5.0 mm × 3.2 mm for CY2X014 and
7.0 mm × 5.0 mm for CY2X0147
Commercial and industrial temperature ranges
Cypress Semiconductor Corporation
Document Number: 001-88287 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 8, 2018
CY2X014
CY2X0147
Logic Block Diagram
4
CRYSTAL
OSCILLATOR
LOW- NOISE
PLL
CLK
OUTPUT
DIVIDER
5
CLK#
Device Type 1: High-performance
LVPECL crystal oscillator with Output
Enable
PROGRAMMABLE
CONFIGURATION
1
OE/PD#
6
V
DD
3
V
SS
4
Device Type 2: High-performance
LVPECL crystal oscillator with
frequency margining - I
2
C control
1
SDA
2
SCL
CRYSTAL
OSCILLATOR
LOW-NOISE
PLL
CLK
OUTPUT
DIVIDER
5
CLK#
PROGRAMMABLE
CONFIGURATION
I
2
C
INTERFACE
Device Type 3:
High-performance LVPECL
crystal oscillator with frequency
margining - Frequency Select
FS1
FS0
1
4
Crystal
Oscillator
Low-Noise PLL
Output
Divider
5
CLK
CLK#
Frequency Select
Decode
2
CRYSTAL
OSC ILLATOR
LOW-NOISE
PLL
OUTPUT
DIVIDER
4
C LK
Device Type 4:
High-performance LVPECL
voltage-controlled crystal
oscillator
VIN
1
5
PROGRAMMABLE
CONFIGURATION
C LK#
OE/PD#
2
6
VDD
3
VSS
Document Number: 001-88287 Rev. *F
Page 2 of 21
CY2X014
CY2X0147
Contents
Pinout ................................................................................ 4
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 5
Device Type 1 ............................................................. 5
Device Type 2 ............................................................. 5
Device Type 3 ............................................................. 5
Device Type 4 ............................................................. 5
Programming Description ............................................... 6
Field-Programmable CY2X014F/CY2X0147F ............. 6
Factory Configured CY2X014/CY2X0147 ................... 6
Programming Variables ................................................... 6
Output Frequency ........................................................ 6
Pin 1: Output Enable (OE) or Power-Down (PD#) ...... 6
Industrial versus Commercial Device Performance .... 6
Absolute Pull Range .................................................... 6
Memory Map ...................................................................... 7
Serial Interface Protocol and Timing ........................... 7
Device Address ........................................................... 8
Data Valid .................................................................... 8
Data Frame ................................................................. 8
Acknowledge Pulse ..................................................... 9
Write Operations ............................................................... 9
Writing Individual Bytes ............................................... 9
Writing Multiple Bytes .................................................. 9
Read Operations ............................................................... 9
Current Address Read ................................................. 9
Random Read ............................................................. 9
Sequential Read .......................................................... 9
Serial Programming Interface
Timing Specifications .................................................... 10
Absolute Maximum Conditions ..................................... 11
Operating Conditions ..................................................... 11
DC Electrical Characteristics ........................................ 12
Termination Circuits ....................................................... 12
AC Electrical Characteristics ........................................ 13
Switching Waveforms .................................................... 14
Typical Output Characteristics ..................................... 15
Ordering Information ...................................................... 16
Possible Configurations ............................................. 16
Ordering Code Definitions ......................................... 16
Package Diagrams .......................................................... 17
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC® Solutions ...................................................... 21
Cypress Developer Community ................................. 21
Technical Support ..................................................... 21
Document Number: 001-88287 Rev. *F
Page 3 of 21
CY2X014
CY2X0147
Pinout
Figure 1. 6-pin Ceramic LCC pinout
Device Type 1: High
Performance LVPECL
Crystal Oscillator with Output
Enable:
Device Type 2: High
Performance LVPECL
Crystal Oscillator with
Frequency Margining - I
2
C
control
Device Type 3: High
Performance LVPECL
Crystal Oscillator with
Frequency Margining -
Frequency Select
Device Type 4: High
Performance LVPECL
Voltage Controlled Crystal
Oscillator
OE/PD# 1
DNU 2
V
SS
3
6 V
DD
5 CLK#
4 CLK
SDA 1
SCLK 2
V
SS
3
6 V
DD
5 CLK#
4 CLK
FS1 1
FS0 2
VSS 3
6 VDD
5 CLK#
4 CLK
VIN 1
OE/PD# 2
VSS 3
6 VDD
5 CLK#
4 CLK
Pin Definitions
6-pin Ceramic LCC
Name
OE/PD#
Device Type 1
1
Device Type 2
N/A
Device Type 3
N/A
Device Type 4
2
I/O Type
CMOS
input
Description
Output enable pin: Active HIGH. If
OE = 1, CLK is enabled.
Power-down pin: Active LOW. If
PD# = 0, the device is powered
down and the clock is disabled. The
functionality
of
this
pin
is
programmable
CLK,
CLK#
DNU
V
DD
V
SS
FS1, FS0
SDA
SCLK
VIN
4,5
2
6
3
N/A
N/A
N/A
N/A
4,5
N/A
6
3
N/A
1
2
N/A
4,5
N/A
6
3
1,2
N/A
N/A
N/A
4,5
N/A
6
3
N/A
N/A
N/A
1
LVPECL Differential output clock
output
–
Power
Power
CMOS
input
I/O
CMOS
input
Analog
input
Do not use: DNU pins are electrically
connected but perform no function
Supply voltage: 2.5 V or 3.3 V
Ground
Frequency Select
I
2
C Serial Data
I
2
C Serial Clock
VCXO control voltage, positive slope
Document Number: 001-88287 Rev. *F
Page 4 of 21
CY2X014
CY2X0147
Functional Overview
Device Type 1
Device Type 1 is a simple crystal oscillator with one output
frequency. Pin 1 can be programmed either as OE or PD#. The
OE function is used to enable or disable the CLK output whereas
the PD# function places the device in a low-power state.
Figure 2. Frequency Words
Register
Address
10h – 15h
16h – 1Bh
1Ch – 21h
22h – 27h
40h
Frequency Word 0
Frequency Word 1
Frequency Word 2
Frequency Word 3
Select Byte
Bits [1:0]
00
01
10
11
Sel
Figure 2
shows how the frequency words are arranged and
selected.
Device Type 2
Device Type 2 has an I
2
C bus serial interface
[1]
, which is used
to change the output frequency.
The CY2X014/CY2X0147 device is configured for four
frequencies. At power-on, the four configurations are
transparently loaded into an internal volatile memory which, in
turn, controls the PLL. The user can switch between the four
frequencies through the I
2
C bus. The user can also configure the
CY2X014/CY2X0147 with new output frequencies by shifting
new data into the internal memory.
Frequency margining is a common application for this feature.
One frequency is used for the standard operating mode of the
device, while additional frequencies are available for margin
testing, either during product development or in-system
manufacturing test.
Note that all configuration changes made using I
2
C are
temporary and are lost when power is removed from the device.
At power-on, the device returns to its original state.
The configuration for a particular frequency is stored in a 6-byte
block of memory, known as a word. The CY2X014/CY2X0147
device has four such words, labeled ‘Frequency Word 0’ through
‘Frequency Word 3’. An additional register byte contains a 2-bit
field, which selects one of the four frequency words. By writing
to this select byte, the user can switch back and forth between
the four programmed frequencies. The select byte can be
configured to select any of the four frequency words at power-on.
When changing the output frequency, the frequency transition is
not guaranteed to be smooth. There can be frequency
excursions beyond the start frequency and the new
frequency.Glitches and runt pulses are possible, and time must
be allowed for the PLL to relock.
If more than four frequencies are needed, the I
2
C bus can be
used to change any of the four frequency words. When writing
frequency words through I
2
C, the users should not change the
currently selected word. Instead, write one of the three
unselected words before changing the select byte to select that
new word.
Control
PLL
Device Type 3
The FS0 and FS1 pins select between four different output
frequencies, as shown in
Table 1.
Frequency margining is a
common application for this feature. One frequency is used for
the standard operating mode of the device, while the other
frequencies are available for margin testing, either during
product development or in-system manufacturing test.
Table 1. Frequency Select
FS1
0
0
1
1
FS0
0
1
0
1
Output Frequency
Frequency 0
Frequency 1
Frequency 2
Frequency 3
When changing the output frequency, the frequency transition is
not guaranteed to be smooth. There can be frequency
excursions beyond the start frequency and the new frequency.
Glitches and runt pulses are possible, and time must be allowed
for the PLL to relock.
Device Type 4
Device Type 4 is a voltage-controlled crystal oscillator. It has a
control voltage pin, VIN, which is an analog input used to adjust
the output frequency. The nominal output frequency is defined
when VIN = VDD,NOM/2. Increasing the voltage on VIN
increases the output frequency, while decreasing the voltage on
VIN decreases the output frequency. Any voltage between VSS
and VDD is allowed on VIN. The voltage or frequency slope is
very linear over most of the control voltage range.
Note
1. The serial interface is I
2
C Bus compliant with the following exceptions: SDA input leakage current, SDA input capacitance, SDA, and SCLK are clamped to V
DD
,
setup time, and output hold time.
Document Number: 001-88287 Rev. *F
Page 5 of 21
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