MSC8254SVT800B datasheet, PDF - EEWORLD Datasheet

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MSC8254SVT800B: DescriptionDigital Signal Processors & Controllers - DSP, DSC DSPStarcore 4-core; Categorysemiconductor The embedded processor and controller; File Size594KB，67 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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Digital Signal Processors & Controllers - DSP, DSC DSPStarcore 4-core

MSC8254SVT800B Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	NXP
Product Category	Digital Signal Processors & Controllers - DSP, DSC
RoHS	Details
Mounting Style	SMD/SMT
Package / Case	PBGA-783
Product	DSPs
Core	SC3850
Maximum Clock Frequency	800 MHz
Program Memory Size	512 kB
Data RAM Size	32 kB
Operating Supply Voltage	1 V
Maximum Operating Temperature	+ 105 C
Packaging	Tray
Program Memory Type	Cache
Interface Type	I2C, SPI
Data Bus Width	32 bit, 64 bit
Moisture Sensitive	Yes
Factory Pack Quantity	1
Unit Weight	0.393340 oz

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Freescale Semiconductor

Data Sheet

Document Number: MSC8254

Rev. 7, 7/2013

MSC8254

Quad-Core Digital Signal

Processor

FC-PBGA–783

29 mm

• Four StarCore SC3850 DSP subsystems, each with an SC3850

DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,

unified 512 Kbyte L2 cache configurable as M2 memory in

64 Kbyte increments, memory management unit (MMU),

extended programmable interrupt controller (EPIC), two

general-purpose 32-bit timers, debug and profiling support,

low-power Wait, Stop, and power-down processing modes, and

ECC/EDC support.

• Chip-level arbitration and switching system (CLASS) that

provides full fabric non-blocking arbitration between the cores

and other initiators and the M2 memory, shared M3 memory,

DDR SRAM controllers, device configuration control and status

registers, and other targets.

• 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can

be turned off to save power.

• 96 Kbyte boot ROM.

• Three input clocks (one global and two differential).

• Five PLLs (three global and two Serial RapidIO PLLs).

• Two DDR controllers with up to a 400 MHz clock (800 MHz data

rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to

four banks (two per controller) and support for DDR2 and DDR3.

• DMA controller with 32 unidirectional channels supporting 16

memory-to-memory channels with up to 1024 buffer descriptors

per channel, and programmable priority, buffer, and multiplexing

configuration. It is optimized for DDR SDRAM.

• Up to four independent TDM modules with programmable word

size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,

up to 62.5 Mbps data rate for each TDM link, and with glueless

interface to E1 or T1 framers that can interface with

H-MVIP/H.110 devices, TSI, and codecs such as AC-97.

• High-speed serial interface that supports two Serial RapidIO

interfaces, one PCI Express interface, and two SGMII interfaces

(multiplexed). The Serial RapidIO interfaces support 1x/4x

operation up to 3.125 Gbaud with a single messaging unit and two

DMA units. The PCI Express controller supports 32- and 64-bit

addressing, x4, x2, and x1 link.

• QUICC Engine technology subsystem with dual RISC

processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction

RAM, supporting two communication controllers for two Gigabit

Ethernet interfaces (RGMII or SGMII), to offload scheduling

tasks from the DSP cores, and an SPI.

• I/O Interrupt Concentrator consolidates all chip maskable

interrupt and non-maskable interrupt sources and routes then to

INT_OUT, NMI_OUT, and the cores.

• UART that permits full-duplex operation with a bit rate of up to

6.25 Mbps.

• Two general-purpose 32-bit timers for RTOS support per SC3850

core, four timer modules with four 16-bit fully programmable

timers, and eight software watchdog timers (SWT).

• Eight programmable hardware semaphores.

• Up to 32 virtual interrupts and a virtual NMI asserted by simple

write access.

• I

C interface.

• Up to 32 GPIO ports, sixteen of which can be configured as

external interrupts.

• Boot interface options include Ethernet, Serial RapidIO interface,

C, and SPI.

• Supports standard JTAG interface

• Low power CMOS design, with low-power standby and

power-down modes, and optimized power-management circuitry.

• 45 nm SOI CMOS technology.

Table of Contents

Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.1 FC-PBGA Ball Layout Diagram . . . . . . . . . . . . . . . . . . . .4

1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .5

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.2 Recommended Operating Conditions . . . . . . . . . . . . . .24

2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .25

2.4 CLKIN Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .26

2.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .26

2.6 AC Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . .36

Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .53

3.1 Power Supply Ramp-Up Sequence. . . . . . . . . . . . . . . .53

3.2 PLL Power Supply Design Considerations . . . . . . . . . .56

3.3 Clock and Timing Signal Board Layout Considerations 57

3.4 SGMII AC-Coupled Serial Link Connection Example . .58

3.5 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .58

3.6 Guide to Selecting Connections for Remote Power

Supply Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 10.SGMII Transmitter DC Measurement Circuit . . . . . . . . . 35

Figure 11.DDR2 and DDR3 SDRAM Interface Input Timing

Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 12.MCK to MDQS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 13.DDR SDRAM Output Timing . . . . . . . . . . . . . . . . . . . . . 39

Figure 14.DDR2 and DDR3 Controller Bus AC Test Load. . . . . . . 40

Figure 15.DDR2 and DDR3 SDRAM Differential Timing

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 16.Differential Measurement Points for Rise and Fall Time 41

Figure 17.Single-Ended Measurement Points for Rise and Fall Time

Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 18.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . 44

Figure 19.SGMII AC Test/Measurement Load . . . . . . . . . . . . . . . . 44

Figure 20.TDM Receive Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 21.TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 22.TDM AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 23.Timer AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 24.MII Management Interface Timing . . . . . . . . . . . . . . . . . 48

Figure 25.RGMII AC Timing and Multiplexing . . . . . . . . . . . . . . . . 49

Figure 26.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 27.SPI AC Timing in Slave Mode (External Clock) . . . . . . . 50

Figure 28.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 51

Figure 29.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 30.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 52

Figure 31.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 32.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 33.Supply Ramp-Up Sequence with V

Ramping Before

DDIO

and CLKIN Starting With V

DDIO

. . . . . . . . . . . . . 54

Figure 34.Supply Ramp-Up Sequence . . . . . . . . . . . . . . . . . . . . . 55

Figure 35.Reset Connection in Functional Application . . . . . . . . . 55

Figure 36.Reset Connection in Debugger Application . . . . . . . . . . 56

Figure 37.PLL Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 38.SerDes PLL Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 39.4-Wire AC-Coupled SGMII Serial Link Connection

Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 40.MSC8254 Mechanical Information, 783-ball FC-PBGA

Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

List of Figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

MSC8254 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3

StarCore SC3850 DSP Subsystem Block Diagram . . . . 3

MSC8254 FC-PBGA Package, Top View . . . . . . . . . . . . 4

Differential Voltage Definitions for Transmitter or

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Receiver of SerDes Reference Clocks . . . . . . . . . . . . . 30

SerDes Transmitter and Receiver Reference Circuits. . 31

Differential Reference Clock Input DC Requirements

(External DC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 31

Differential Reference Clock Input DC Requirements

(External AC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 32

Single-Ended Reference Clock Input DC Requirements 32

MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 7

Freescale Semiconductor

MSC8254SVT800B Related Products

	MSC8254SVT800B	MSC8254TVT800B
Description	Digital Signal Processors & Controllers - DSP, DSC DSPStarcore 4-core	Digital Signal Processors & Controllers - DSP, DSC DSPStarcore 4-core
Product Attribute	Attribute Value	Attribute Value
Manufacturer	NXP	NXP
Product Category	Digital Signal Processors & Controllers - DSP, DSC	Digital Signal Processors & Controllers - DSP, DSC
RoHS	Details	Details
Mounting Style	SMD/SMT	SMD/SMT
Package / Case	PBGA-783	PBGA-783
Product	DSPs	DSPs
Core	SC3850	SC3850
Maximum Clock Frequency	800 MHz	800 MHz
Program Memory Size	512 kB	512 kB
Data RAM Size	32 kB	32 kB
Operating Supply Voltage	1 V	1 V
Maximum Operating Temperature	+ 105 C	+ 105 C
Packaging	Tray	Tray
Program Memory Type	Cache	Cache
Interface Type	I2C, SPI	I2C, SPI
Data Bus Width	32 bit, 64 bit	32 bit, 64 bit
Moisture Sensitive	Yes	Yes
Factory Pack Quantity	1	1
Unit Weight	0.393340 oz	0.393340 oz

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