gramming the Variable Resistor Section .......................... 13
Rev. E | Page 2 of 32
AD8400/AD8402/AD8403
GENERAL DESCRIPTION
(continued from Page 1)
Each VR has its own VR latch that holds its programmed
resistance value. These VR latches are updated from an SPI-
compatible, serial-to-parallel shift register that is loaded from
a standard 3-wire, serial-input digital interface. Ten data bits
make up the data-word clocked into the serial input register.
The data-word is decoded where the first two bits determine
the address of the VR latch to be loaded, and the last eight bits
are the data. A serial data output pin at the opposite end of the
serial register allows simple daisy chaining in multiple VR
applications without additional external decoding logic.
The reset (RS) pin forces the wiper to midscale by loading 80
H
into the VR latch. The SHDN pin forces the resistor to an end-
to-end open-circuit condition on the A terminal and shorts the
wiper to the B terminal, achieving a microwatt power shutdown
state. When SHDN is returned to logic high, the previous latch
settings put the wiper in the same resistance setting prior to
shutdown. The digital interface is still active in shutdown so
that code changes can be made that will produce new wiper
positions when the device is taken out of shutdown.
The AD8400 is available in the SOIC-8 surface mount. The
AD8402 is available in both surface-mount (SOIC-14) and
14-lead PDIP packages, while the AD8403 is available in a
narrow-body, 24-lead PDIP and a 24-lead, surface-mount
package. The AD8402/AD8403 are also offered in the 1.1 mm
thin TSSOP-14/TSSOP-24 packages for PCMCIA applications.
All parts are guaranteed to operate over the extended industrial
temperature range of −40°C to +125°C.
Rev. E | Page 3 of 32
AD8400/AD8402/AD8403
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—10 KΩ VERSION
V
DD
= 3 V ± 10% or 5 V ± 10%, V
A
= V
DD
, V
B
= 0 V, −40°C ≤ T
A
≤ +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL
2
R-DNL
R
WB
, V
A
= no connect
2
Resistor Nonlinearity
R-INL
R
WB
, V
A
= no connect
3
Nominal Resistance
R
AB
T
A
= 25°C, model: AD840XYY10
Resistance Tempco
ΔR
AB
/ΔT
V
AB
= V
DD
, wiper = no connect
Wiper Resistance
R
W
V
DD
= 5V, I
W
= V
DD
/R
AB
R
W
V
DD
= 3V, I
W
= V
DD
/R
AB
Nominal Resistance Match
ΔR/R
AB
CH 1 to CH 2, CH 3, or CH 4, V
AB
= V
DD
, T
A
= 25°C
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution
N
4
Integral Nonlinearity
INL
4
Differential Nonlinearity
DNL
V
DD
= 5 V
DNL
V
DD
= 3 V, T
A
= 25°C
DNL
V
DD
= 3 V, T
A
= −40°C to +85°C
Voltage Divider Tempco
ΔV
W
/ΔT
Code = 80
H
Full-Scale Error
V
WFSE
Code = FF
H
Zero-Scale Error
V
WZSE
Code = 00
H
RESISTOR TERMINALS
Voltage Range
5
V
A, B, W
6
Capacitance Ax, Capacitance Bx C
A, B
f = 1 MHz, measured to GND, code = 80
H
6
Capacitance Wx
C
W
f = 1 MHz, measured to GND, code = 80
H
7
Shutdown Current
I
A_SD
V
A
= V
DD
, V
B
= 0 V, SHDN = 0
Shutdown Wiper Resistance
R
W_SD
V
A
= V
DD
, V
B
= 0 V, SHDN = 0, V
DD
= 5 V
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
V
DD
= 5 V
Input Logic Low
V
IL
V
DD
= 5 V
Input Logic High
V
IH
V
DD
= 3 V
Input Logic Low
V
IL
V
DD
= 3 V
Output Logic High
V
OH
R
L
= 2.2 kΩ to V
DD
Output Logic Low
V
OL
I
OL
= 1.6 mA, V
DD
= 5 V
Input Current
I
IL
V
IN
= 0 V or 5 V, V
DD
= 5 V
Input Capacitance
6
C
IL
POWER SUPPLIES
Power Supply Range
V
DD
range
Supply Current (CMOS)
I
DD
V
IH
= V
DD
or V
IL
= 0 V
Supply Current (TTL)
8
I
DD
V
IH
= 2.4 V or 0.8 V, V
DD
= 5.5 V
9
Power Dissipation (CMOS)
P
DISS
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= 5.5 V
Power Supply Sensitivity
PSS
V
DD
= 5 V ± 10%
PSS
V
DD
= 3 V ± 10%
Min
−1
−2
8
Typ
1
±1/4
±1/2
10
500
50
200
0.2
Max
+1
+2
12
100
1
Unit
LSB
LSB
kΩ
ppm/°C
Ω
Ω
%
Bits
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
μA
Ω
V
V
V
V
V
V
μA
pF
V
μA
mA
μW
%/%
%/%
8
−2
−1
−1
−1.5
−4
0
0
±1/2
±1/4
±1/4
±1/2
15
−2.8
1.3
+2
+1
+1
+1.5
0
2
V
DD
75
120
0.01
100
2.4
5
200
0.8
2.1
0.6
V
DD
− 0.1
0.4
±1
5
2.7
0.01
0.9
0.0002
0.006
5.5
5
4
27.5
0.001
0.03
Rev. E | Page 4 of 32
AD8400/AD8402/AD8403
Parameter
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth −3 dB
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage
Crosstalk
11
1
2
Symbol
BW_10 K
THD
W
t
S
e
NWB
C
T
Conditions
R = 10 kΩ
V
A
= 1 V rms + 2 V dc, V
B
= 2 V dc, f = 1 kHz
V
A
= V
DD
, V
B
= 0 V, ±1% error band
R
WB
= 5 kΩ, f = 1 kHz, RS = 0
V
A
= V
DD
, V
B
= 0 V
Min
Typ
1
600
0.003
2
9
−65
Max
Unit
kHz
%
μs
nV/√Hz
dB
Typical represents average readings at 25°C and V
DD
= 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.
I
W
= 50 μA for V
DD
= 3 V and I
W
= 400 μA for V
DD
= 5 V for the 10 kΩ versions.
3
V
AB
= V
DD
, wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of I
DD
vs. logic voltage.
9
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
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