Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 4
Chapter 2. Functional Description ........................................................................................................ 6
XAUI IP Core I/O................................................................................................................................................... 9
Functional Description......................................................................................................................................... 10
XGMII and Slip Buffers............................................................................................................................... 14
XAUI-to-XGMII Translation (Receive Interface) ......................................................................................... 15
XGMII-to-XAUI Translation (Transmit Interface) ........................................................................................ 16
Management Data Input/Output (MDIO) Interface (Optional) .................................................................... 18
Management Frame Structure ................................................................................................................... 19
Register Descriptions .......................................................................................................................................... 20
Input/Output Timing............................................................................................................................................. 22
XGMII Specifications.................................................................................................................................. 22
XAUI Specifications.................................................................................................................................... 24
MDIO Specifications................................................................................................................................... 24
Chapter 3. Parameter Settings ............................................................................................................ 25
XAUI IP Configuration Dialog Box....................................................................................................................... 25
Parameter Descriptions....................................................................................................................................... 25
Tx Slip Buffer.............................................................................................................................................. 25
Rx Slip Buffer ............................................................................................................................................. 26
MDIO.......................................................................................................................................................... 26
Behavioral Model ....................................................................................................................................... 26
Netlist [.ngo] ............................................................................................................................................... 26
Evaluation Directory ................................................................................................................................... 26
Tools Support............................................................................................................................................. 26
Chapter 4. IP Core Generation............................................................................................................. 27
Licensing the IP Core.......................................................................................................................................... 27
Getting Started .................................................................................................................................................... 27
IPexpress-Created Files and Top Level Directory Structure............................................................................... 29
Instantiating the Core ................................................................................................................................. 30
Running Functional Simulation .................................................................................................................. 31
Synthesizing and Implementing the Core in a Top-Level Design .............................................................. 31
Hardware Evaluation........................................................................................................................................... 32
Enabling Hardware Evaluation in Diamond................................................................................................ 32
Enabling Hardware Evaluation in ispLEVER.............................................................................................. 32
Updating/Regenerating the IP Core .................................................................................................................... 33
Regenerating an IP Core in Diamond ........................................................................................................ 33
Regenerating an IP Core in ispLEVER ...................................................................................................... 33
Chapter 5. Support Resources ............................................................................................................ 35
Lattice Technical Support.................................................................................................................................... 35
Online Forums............................................................................................................................................ 35
Telephone Support Hotline ........................................................................................................................ 35
E-mail Support ........................................................................................................................................... 35
Local Support ............................................................................................................................................. 35
Internet ....................................................................................................................................................... 35
References.......................................................................................................................................................... 35
LatticeECP3 ............................................................................................................................................... 35
LatticeECP2M ............................................................................................................................................ 35
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Lattice Semiconductor
Table of Contents
Revision History .................................................................................................................................................. 36
............................................................................................................................................................................ 36
Appendix A. Resource Utilization ....................................................................................................... 37
LatticeECP2M FPGAs......................................................................................................................................... 37
Ordering Part Number................................................................................................................................ 37
Jitter and XAUI Compliance ....................................................................................................................... 37
LatticeECP3 FPGAs............................................................................................................................................ 38
Ordering Part Number................................................................................................................................ 38
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XAUI IP Core User’s Guide
Chapter 1:
Introduction
The 10Gb Ethernet Attachment Unit Interface (XAUI) IP Core User’s Guide for the LatticeECP2M™ and
LatticeECP3™ FPGAs provides a solution for bridging between XAUI and 10-Gigabit Media Independent Interface
(XGMII) devices. This IP core implements 10Gb Ethernet Extended Sublayer (XGXS) capabilities in soft logic that
together with PCS and SERDES functions implemented in the FGPA provides a complete XAUI-to-XGMII solution.
The XAUI IP core package comes with the following documentation and files:
• Protected netlist/database
• Behavioral RTL simulation model
• Source files for instantiating and evaluating the core
The XAUI IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of
the IP core that operate in hardware for a limited period of time (approximately four hours) without requiring the pur-
chase on an IP license. It may also be used to evaluate the core in hardware in user-defined designs. Details for
using the hardware evaluation capability are described in the Hardware Evaluation section of this document.
Quick Facts
Table 1-1
gives quick facts about the XAUI IP core.
Table 1-1. XAUI IP Core Quick Facts
XAUI IP Configuration
Across All IP configurations
FPGA Families Supported
Core Requirements
Minimal Device Supported
Data Path Width
LUTs
Resource Utilization
sysMEM EBRs
Registers
Lattice Implementation
Synthesis
Design Tool Support
Simulation
Mentor Graphics ModelSim™ SE 6.3F (Verilog only)
0-4
1500-2700
0-4
1500-2700
LFE3-17E-7FN256C
72 bits
1700-2700
LFE2M20E-6F256C
72 bits
1800-2800
Lattice ECP3, Lattice ECP2M
Diamond
®
1.0 or ispLEVER
®
8.1
Synopsys
®
Synplify™ Pro for Lattice D-2009.12L-1
Mentor Graphics
®
Precision™ RTL
Aldec
®
Active-HDL™ 8.2 Lattice Edition
Features
• XAUI compliant functionality supported by embedded SERDES PCS functionality implemented in the
LatticeECP2M and LatticeECP3, including four channels of 3.125 Gbps serializer/deserializer with 8b10b encod-
ing/decoding.
• Complete 10Gb Ethernet Extended Sublayer (XGXS) solution based on LatticeECP2M and LatticeECP3 FPGA.
• Soft IP targeted to the FPGA implements XGXS functionality conforming to IEEE 802.3-2005, including:
– 10 GbE Media Independent Interface (XGMII).
– Optional slip buffers for clock domain transfer to/from the XGMII interface.
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Microcontroller MCU
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