SN74LV32ADGVRE4 datasheet, PDF

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SN74LV32ADGVRE4: DescriptionLogic Gates Quadruple 2-Input Positive-OR Gates; Categorylogic logic; File Size1MB，28 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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SN74LV32ADGVRE4 Overview

Logic Gates Quadruple 2-Input Positive-OR Gates

SN74LV32ADGVRE4 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	SOIC
package instruction	TSSOP, TSSOP14,.25
Contacts	14
Reach Compliance Code	unknown
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	4.4 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	OR GATE
MaximumI(ol)	0.006 A
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TR
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	13 ns
propagation delay (tpd)	19 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.6 mm
Base Number Matches	1

SN74LV32ADGVRE4 Related Products

	SN74LV32ADGVRE4	SN74LV32ARGYRG4	SN74LV32APWG4	SN74LV32APWTG4	SN74LV32APWTE4	SN74LV32ADBRG4	SN74LV32ADGVRG4
Description	Logic Gates Quadruple 2-Input Positive-OR Gates	Logic Gates Quad 2-Input Pos	Logic Gates Quadruple 2-Input Positive-OR Gates	Logic Gates Quadruple 2-Input Positive-OR Gates	Logic Gates Quadruple 2-Input Positive-OR Gates	Logic Gates Quad 2 Input Pos OR Gates	Logic Gates Quad 2 Input Pos OR Gates
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Parts packaging code	SOIC	QFN	TSSOP	TSSOP	TSSOP	SSOP	SOIC
package instruction	TSSOP, TSSOP14,.25	HVQCCN, LCC14/18,.14SQ,20	TSSOP, TSSOP14,.25	TSSOP, TSSOP14,.25	TSSOP, TSSOP14,.25	SSOP, SSOP14,.3	TSSOP, TSSOP14,.25
Contacts	14	14	14	14	14	14	14
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
series	LV/LV-A/LVX/H	LV/LV-A/LVX/H	-	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14	S-PQCC-N14	-	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e4	e4	-	e4	e4	e4	e4
length	4.4 mm	3.5 mm	-	5 mm	5 mm	6.2 mm	4.4 mm
Load capacitance (CL)	50 pF	50 pF	-	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	OR GATE	OR GATE	-	OR GATE	OR GATE	OR GATE	OR GATE
MaximumI(ol)	0.006 A	0.006 A	-	0.006 A	0.006 A	0.006 A	0.006 A
Humidity sensitivity level	1	2	-	1	1	1	1
Number of functions	4	4	-	4	4	4	4
Number of entries	2	2	-	2	2	2	2
Number of terminals	14	14	-	14	14	14	14
Maximum operating temperature	85 °C	85 °C	-	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	HVQCCN	-	TSSOP	TSSOP	SSOP	TSSOP
Encapsulate equivalent code	TSSOP14,.25	LCC14/18,.14SQ,20	-	TSSOP14,.25	TSSOP14,.25	SSOP14,.3	TSSOP14,.25
Package shape	RECTANGULAR	SQUARE	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TR	TAPE AND REEL	-	TR	TR	TAPE AND REEL	TR
Peak Reflow Temperature (Celsius)	260	260	-	260	260	260	260
power supply	3.3 V	3.3 V	-	3.3 V	3.3 V	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	13 ns	13 ns	-	13 ns	13 ns	13 ns	13 ns
propagation delay (tpd)	19 ns	19 ns	-	19 ns	19 ns	19 ns	19 ns
Certification status	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	-	NO	NO	NO	NO
Maximum seat height	1.2 mm	1 mm	-	1.2 mm	1.2 mm	2 mm	1.2 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	-	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	2 V	2 V	-	2 V	2 V	2 V	2 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	-	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	-	YES	YES	YES	YES
technology	CMOS	CMOS	-	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	-	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	NO LEAD	-	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.4 mm	0.5 mm	-	0.65 mm	0.65 mm	0.65 mm	0.4 mm
Terminal location	DUAL	QUAD	-	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	3.6 mm	3.5 mm	-	4.4 mm	4.4 mm	5.3 mm	3.6 mm
Maker	-	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments

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