TC9WMA2FK
TOSHIBA CMOS Digital Integrated Circuits
Silicon Monolithic
TC9WMA2FK
2,048-Bit (256 × 8 Bit) Serial E
2
PROM
The TC9WMA2FK is electrically erasable/programmable
nonvolatile memory (E
2
PROM).
Features
•
•
•
•
•
•
•
•
•
Serial data input/output
Programmable in units of one word and collectively erasable
in one operation
Automatically set programming time (built-in timer)
Programming time: 10 ms (max) (V
CC
= 3.0 to 5.5 V)
12 ms (max) (V
CC
= 2.3 to 2.7 V)
Overwrite enabled or disabled by software
Single power supply and low power consumption
Operating voltage range for reading: V
CC
= 1.8 to 5.5 V
Operating voltage range for writing: V
CC
= 2.3 to 5.5 V
Wide operating temperature range (−40 to 85°C)
Weight: 0.01 g (typ.)
Product Marking
US8
Type name
Pin Assignment
(top view)
CS
CLK
DI
6
8
7
DO
5
9WM
A2
No.1 pin indicator
1
2
3
4
V
CC
NC
RST
GND
1
2007-10-19
TC9WMA2FK
Block Diagram
Chip select
CS
Clock input
Timing
generator
Control
circuit
Power supply
(booster circuit)
V
CC
Power supply
Reset input
RST
CLK
Command
register
Input/Output
circuit
Data Output DO
Memory cell
Address Address
register decoder
Data Input DI
GND Ground
Data register
Pin Function
Pin Name
Input/Output
Input
Function
Chip select
A low on
CS
selects the chip. Always return
CS
high temporarily before
executing instructions.
Clock input
The data on DI is latched by a rising edge of CLK . Data is output to DO by a falling
edge of CLK . CLK is effective when CS is low.
Serial data input
This pin is used to enter addresses, commands, and data into the chip.
Serial data output
This pin outputs data from the chip.
Reset input
A low on this input resets the chip.
No connection (not connected internally)
1.8 V~5.5 V (for reading)
2.3~5.5 V (for writing)
0 V (GND)
CS
CLK
Input
DI
DO
RST
NC
V
CC
GND
Input
Output
Input
⎯
Power supply
2
2007-10-19
TC9WMA2FK
Functional Description
1. Types of Instructions
Operation
Read
Program
All erase
Busy monitor
Overwrite enable
Overwrite disable
Read Auto-incremented
Address
A0~A7
A0~A7
********
********
********
********
Command
C0 C1 C2 C3
1
0
0
1
1
1
1
0
1
0
0
0
1
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data
D0~D7
A0~A7
*:
Don’t care
2. Operation Method
Be sure to drive
CS
and
CLK
high temporarily before entering an instruction. After
CS
is asserted
low,
CLK
becomes effective, acting as a serial transfer synchronizing signal. The data on DI is latched on
a rising edge of
CLK
, while data is output to DO on a falling edge of
CLK
.
Instructions can only be executed when the chip is not being programmed or collectively erased (i.e.,
when the ready/busy status signal is high). However, the Monitor Busy instruction can be entered at any
time.
Only the commands listed in the above table can be used. Do not use any other command.
•
Read
Entering the Read instruction causes memory data at the specified address to be read out and serially
output from the DO pin.
•
Program
Entering the Program instruction causes overwrite operation to automatically start within the chip,
overwriting memory data at the specified address with the input data.
After the instruction is entered,
CS
can be driven high even while overwrite operation is still in
progress internally.
•
All Erase
Entering the Erase All instruction causes erase operation to automatically start within the chip,
erasing memory data at all addresses.
After the instruction is entered,
CS
can be driven high even while erase operation is still in progress
internally.
This command clears the memory data to 0.
•
Busy Monitor
Entering the Monitor Busy instruction causes a ready/busy status signal to be output from the DO pin.
This output signal is low while the chip is being programmed or collectively erased, and is high after
programming or collective erase operation is completed.
The ready/busy status signal is output continuously until
CS
is driven high.
•
Overwrite Enable/Disable
Entering the Enable Overwrite instruction places the chip in overwrite enabled mode, where the
Program and Erase All instructions can be entered.
Entering the Disable Overwrite instruction places the chip in overwrite disabled mode, where the
Program and Erase All instructions cannot be entered.
Once the chip is placed in overwrite disabled mode, it remains disabled against overwriting until the
Enable Overwrite instruction is entered.
•
Read Auto-incremented
After the data at the specified address is output, the subsequent
CLK
pulse causes the address to be
incremented so that the data at the next address is output automatically. After the data at the last
address is output, that at the first address will be read and output.
3
2007-10-19
FPGA/CPLD
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