TC59LM836DKB-40 datasheet, PDF

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TC59LM836DKB-40: DescriptionMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2; Categorystorage storage; File Size737KB，65 Pages; ManufacturerToshiba Semiconductor; Websitehttp://toshiba-semicon-storage.com/

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TC59LM836DKB-40 Overview

MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2

TC59LM836DKB-40 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Toshiba Semiconductor
Parts packaging code	BGA
package instruction	TBGA,
Contacts	144
Reach Compliance Code	unknow
access mode	FOUR BANK PAGE BURST
Maximum access time	0.6 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B144
length	18.5 mm
memory density	301989888 bi
Memory IC Type	DDR DRAM
memory width	36
Number of functions	1
Number of ports	1
Number of terminals	144
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	8MX36
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	MOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	11 mm

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TC59LM836DKB-30,-33,-40

TENTATIVE

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

288Mbits Network FCRAM2

−

2,097,152-WORDS

4 BANKS

36-BITS

DESCRIPTION

Network FCRAM

is Double Data Rate Fast Cycle Random Access Memory. TC59LM836DKB is Network

FCRAM

containing 301,989,888 memory cells. TC59LM836DKB is organized as 2,097,152-words

4 banks

bits. TC59LM836DKB feature a fully synchronous operation referenced to clock edge whereby all operations are

synchronized at a clock input which enables high performance and simple user interface coexistence.

TC59LM836DKB can operate fast core cycle compared with regular DDR SDRAM.

TC59LM836DKB is suitable for Network and other applications where large memory density and low power

consumption are required. The Output Driver for Network FCRAM

is capable of high quality fast data transfer

under light loading condition.

FEATURES

PARAMETER

-30

RAC

Clock Cycle Time (min)

Random Read/Write Cycle Time (min)

Random Access Time (max)

4.0 ns

3.5 ns

3.0 ns

20.0 ns

380 mA

100 mA

15 mA

TC59LM836DKB

-33

4.5 ns

3.75 ns

3.33 ns

22.5 ns

360 mA

95 mA

15 mA

-40

5.0 ns

4.5 ns

4.0 ns

25 ns

340 mA

90 mA

15 mA

DD1S

Operating Current (single bank) (max)

DD2P

Power Down Current (max)

DD6

Self-Refresh Current (max)

•

Fully Synchronous Operation

•

Double Data Rate (DDR)

Data input/output are synchronized with both edges of DS / QS.

•

Differential Clock (CLK and

CLK

) inputs

, FN and all address input signals are sampled on the positive edge of CLK.

Output data (DQs and QS) is aligned to the crossings of CLK and

CLK

Fast clock cycle time of 3.0 ns minimum

Clock: 333 MHz maximum

Data: 666 Mbps/pin maximum

Quad Independent Banks operation

Fast cycle and Short Latency

Selectable Data Strobe

Distributed Auto-Refresh cycle in 3.9

µs

Self-Refresh

Power Down Mode

Variable Write Length Control

Write Latency

CAS

Latency-1

Programable

CAS

Latency and Burst Length

CAS

Latency

4, 5, 6

Burst Length

2, 4

Organization: 2,097,152 words

4 banks

36 bits

Power Supply Voltage

2.5 V

0.125V

DDQ

: 1.4 V ~ 1.9 V

Low voltage CMOS I/O covered with SSTL_18 (Half strength driver) and HSTL.

JTAG boundary scan

Package: 144Ball BGA, 1mm

0.8mm Ball pitch (P-TFBGA144-1119-0.80BZ)

Notice: FCRAM is trademark of Fujitsu limited, Japan.

Rev 1.3

2005-03-07

1/65

TC59LM836DKB-40 Related Products

	TC59LM836DKB-40	TC59LM836DKB-30	TC59LM836DKB-33
Description	MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2	MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2	MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	Toshiba Semiconductor	Toshiba Semiconductor	Toshiba Semiconductor
Parts packaging code	BGA	BGA	BGA
package instruction	TBGA,	TBGA,	TBGA,
Contacts	144	144	144
Reach Compliance Code	unknow	unknow	unknow
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	0.6 ns	0.5 ns	0.5 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144
length	18.5 mm	18.5 mm	18.5 mm
memory density	301989888 bi	301989888 bi	301989888 bi
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM
memory width	36	36	36
Number of functions	1	1	1
Number of ports	1	1	1
Number of terminals	144	144	144
word count	8388608 words	8388608 words	8388608 words
character code	8000000	8000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C
organize	8MX36	8MX36	8MX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TBGA	TBGA	TBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES
Maximum supply voltage (Vsup)	2.625 V	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES
technology	MOS	MOS	MOS
Temperature level	OTHER	OTHER	OTHER
Terminal form	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
width	11 mm	11 mm	11 mm
ECCN code	-	EAR99	EAR99

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