74ACTQ16245 16-Bit Transceiver with 3-STATE Outputs
May 1991
Revised May 2005
74ACTQ16245
16-Bit Transceiver with 3-STATE Outputs
General Description
The ACTQ16245 contains sixteen non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for bus
oriented applications. The device is byte controlled. Each
has separate control inputs which can be shorted together
for full 16-bit operation. The T/R inputs determine the direc-
tion of data flow through the device. The OE inputs disable
both the A and B ports by placing them in a high imped-
ance state.
The ACTQ16245 utilizes Fairchild Quiet Series
¥
technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series
¥
fea-
tures GTO
¥
output control for superior performance.
Features
s
Utilizes Fairchild FACT Quiet Series technology
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin output skew
s
Bidirectional non-inverting buffers
s
Separate control logic for each byte
s
16-bit version of the ACTQ245
s
Outputs source/sink 24 mA
s
Additional specs for multiple output switching
s
Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number
74ACTQ16245SSC
74ACTQ16245MTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Description
Pin Names
OE
n
T/R
A
0
–A
15
B
0
–B
15
Description
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs/Outputs
Side B Outputs/Inputs
FACT
¥
, FACT Quiet Series
¥
and GTO
¥
are trademarks of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS010926
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74ACTQ16245
Functional Description
The ACTQ16245 contains sixteen non-inverting bidirec-
tional buffers with 3-STATE outputs. The device is byte
controlled with each byte functioning identically, but inde-
pendent of the other. The control pins can be shorted
together to obtain full 16-bit operation. The following
description applies to each byte. When the T/R input is
HIGH, then Bus A data is transmitted to Bus B. When the
T/R input is LOW, Bus B data is transmitted to Bus A. The
3-STATE outputs are controlled by an Output Enable (OE
n
)
input for each byte. When OE
n
is LOW, the outputs are in
2-state mode. When OE
n
is HIGH, the outputs are in the
high impedance mode, but this does not interfere with
entering new data into the inputs.
Truth Tables
Inputs
Outputs
OE
1
L
L
H
Inputs
Outputs
OE
2
L
L
H
T/R
2
L
H
X
Bus B
8
–B
15
Data to Bus A
8
–A
15
Bus A
8
–A
15
Data to Bus B
8
–B
15
HIGH-Z State on A
8
–A
15
, B
8
–B
15
T/R
1
L
H
X
Bus B
0
–B
7
Data to Bus A
0
–A
7
Bus A
0
–A
7
Data to Bus B
0
–B
7
HIGH-Z State on A
0
–A
7
, B
0
–B
7
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Logic Diagram
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2
74ACTQ16245
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
V
I
V
O
V
O
0.5V to
7.0V
20 mA
20 mA
20 mA
20 mA
0.5V to V
CC
0.5V
r
50 mA
r
50 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
V/
'
t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
¥
circuits outside databook specifications.
4.5V to 5.5V
0V to V
CC
0V to V
CC
0.5V
V
CC
0.5V
0.5V
V
CC
0.5V
DC Output Diode Current (I
OK
)
40
q
C to
85
q
C
125 mV/ns
DC Output Voltage (V
O
)
DC Output Source/Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin
Storage Temperature
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Minimum HIGH
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
Parameter
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW
Output Voltage
4.5
5.5
4.5
5.5
I
OZT
I
IN
I
CCT
I
CC
I
OLD
I
OHD
V
OLP
V
OLV
V
OHP
V
OHV
V
IHD
V
ILD
Maximum I/O
Leakage Current
Maximum Input Leakage Current
Maximum I
CC
/Input
Max Quiescent Supply Current
Minimum Dynamic
Output Current (Note 3)
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Maximum
Overshoot
Minimum
V
CC
Droop
Minimum HIGH Dynamic Input Voltage Level
Maximum LOW Dynamic Input Voltage Level
5.5
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
5.0
5.0
0.5
0.8
0.6
8.0
0.001
0.001
T
A
Typ
1.5
1.5
1.5
1.5
4.49
5.49
25
q
C
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
T
A
40
q
C to
85
q
C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
Guaranteed Limits
Units
V
V
V
V
OUT
V
OUT
Conditions
0.1V
0.1V
or V
CC
0.1V
or V
CC
0.1V
I
OUT
V
IN
50
P
A
V
IL
or V
IH
V
I
OH
=
24 mA
I
OH
=
24 mA (Note 2)
V
I
OUT
V
IN
50
P
A
V
IL
or V
IH
V
I
OL
= 24 mA
I
OL
= 24 mA (Note 2)
V
I
V
O
V
I
V
I
V
IN
V
OLD
V
OHD
V
IL
, V
IH
V
CC
, GND
V
CC
, GND
V
CC
2.1V
V
CC
or GND
1.65V Max
3.85V Min
r
0.5
r
0.1
r
5.0
r
1.0
1.5
80.0
75
P
A
P
A
mA
P
A
mA
mA
V
V
V
V
V
V
75
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 4)(Note 6)
Figure 1, Figure 2
(Note 4)(Note 6)
(Note 4)(Note 7)
(Note 4)(Note 7)
0.5
0.85
V
OH
1.0 V
OH
1.5
V
OH
1.0 V
OH
1.8
1.7
1.2
2.0
0.8
Note 2:
All outputs loaded; thresholds associated with output under test.
Note 3:
Maximum test duration 2.0 ms; one output loaded at a time.
Note 4:
Worst case package.
Note 5:
Maximum number of outputs that can switch simultaneously is n. (n
1) outputs are switched LOW and one output held LOW.
Note 6:
Maximum number of outputs that can switch simultaneously is n. (n
1) outputs are switched HIGH and one output held HIGH.
Note 7:
Max number of data inputs (n) switching. (n
1) input switching 0V to 3V input under test switching 3V to threshold (V
ILD
)
3
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74ACTQ16245
AC Electrical Characteristics
V
CC
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Propagation Delay
A
n
, B
n
to B
n
, A
n
Output Enable
Time
Output Disable
Time
(V)
(Note 8)
5.0
5.0
5.0
5.0
5.0
5.0
Min
3.2
2.6
3.7
4.1
2.2
2.0
T
A
C
L
25
q
C
50 pF
Typ
5.7
5.1
6.4
7.4
5.4
5.2
Max
8.4
7.9
9.4
10.5
8.7
8.2
T
A
40
q
C to
85
q
C
C
L
50 pF
Max
9.0
8.4
10.0
11.6
9.3
8.8
ns
ns
ns
Units
Min
3.2
2.6
2.7
3.4
2.2
2.0
Note 8:
Voltage Range 5.0 is 5.0V
r
0.5V.
Extended AC Electrical Characteristics
T
A
40
q
C to
85
q
C
C
L
50 pF
T
A
40
q
C to
85
q
C
C
L
250 pF
Units
(Note 12)
Symbol
Parameter
V
CC
(V)
(Note 9)
16 Outputs Switching
(Note 11)
Min
4.2
3.5
4.5
4.4
3.5
3.1
Typ
Max
11.9
9.9
11.4
12.2
9.3
8.8
1.2
1.3
3.0
Min
5.9
5.0
Max
14.6
13.4
ns
ns
ns
ns
ns
ns
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PZL
t
OSHL
(Note 10)
t
OSLH
(Note 10)
t
OST
(Note 10)
Propagation Delay
Data to Output
Output Enable Time
Output Disable Time
Pin to Pin Skew
HL Data to Output
Pin to Pin Skew
LH Data to Output
Pin to Pin Skew
LH/HL Data to Output
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
(Note 13)
(Note 14)
Note 9:
Voltage Range 5.0 is 5.0V
r
0.5V.
Note 10:
Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (t
OST
).
Note 11:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 12:
This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 13:
3-STATE delays are load dominated and have been excluded from the datasheet.
Note 14:
The Output Disable Time is dominated by the RC network (500
:
, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Pin Capacitance
Power Dissipation Capacitance
Typ
4.5
25
Units
pF
pF
V
CC
V
CC
5.0V
5.0V
Conditions
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4
74ACTQ16245
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500
:
.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
V
OLP
/V
OLV
and V
OHP
/V
OHV
:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50
:
coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
• Measure V
OLP
and V
OLV
on the quiet output during the
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case active and enable transition.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
ILD
and V
IHD
:
• Monitor one of the switching outputs using a 50
:
coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, V
IL
, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
• Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
3 ns,
V
OHV
and V
OLP
are measured with respect to ground reference.
Input pulses have the following characteristics: f
t
f
3 ns, skew
150 ps.
1 MHz, t
r
FIGURE 1. Quiet Output Noise Voltage Waveforms
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
FIGURE 2. Simultaneous Switching Test Circuit
5
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