TECHNICAL DATA
KK74AC174
Hex D Flip-Flop with
Common Clock and Reset
High-Speed Silicon-Gate CMOS
The KK74AC174 is identical in pinout to the LS/ALS174,
HC/HCT174. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS outputs.
This device consists of six D flip-flops with common Clock and Reset
inputs. Each flip-flop is loaded with a low-to-high transition of the Clock
input. Reset is asynchronous and active-low.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA;
0.1
µA
@ 25°C
•
High Noise Immunity Characteristic of CMOS Devices
•
Outputs Source/Sink 24mA
ORDERING INFORMATION
KK74AC174N Plastic
KK74AC174D SOIC
T
A
= -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Reset
L
PIN 16=V
CC
PIN 8 = GND
H
H
H
H
X = Don’t care
L
Clock
X
D
X
H
L
X
X
Output
Q
L
H
L
no change
no change
1
KK74AC174
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
±20
±50
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
J
T
A
I
OH
I
OL
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Junction Temperature (PDIP)
Operating Temperature, All Package Types
Output Current - High
Output Current - Low
Input Rise and Fall Time
*
(except Schmitt Inputs)
V
CC
=3.0 V
V
CC
=4.5 V
V
CC
=5.5 V
0
0
0
-40
Min
2.0
0
Max
6.0
V
CC
140
+85
-24
24
150
40
25
Unit
V
V
°C
°C
mA
mA
ns/V
*
V
IN
from 30% to 70% V
CC
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
2
KK74AC174
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
V
IH
Parameter
Minimum High-
Level Input Voltage
Maximum Low -
Level Input Voltage
Minimum High-
Level Output Voltage
Test Conditions
V
OUT
=0.1 V or V
CC
-0.1 V
V
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
5.5
5.5
5.5
8.0
Guaranteed Limits
25
°C
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
-40°C to
85°C
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
75
-75
80
µA
mA
mA
µA
V
Unit
V
V
IL
V
OUT
=0.1 V or V
CC
-0.1 V
V
V
OH
I
OUT
≤
-50
µA
V
V
IN
=V
IH
or V
IL
I
OH
=-12 mA
I
OH
=-24 mA
I
OH
=-24 mA
V
OL
Maximum Low-
Level Output Voltage
I
OUT
≤
50
µA
*
*
V
IN
=V
IH
or V
IL
I
OL
=12 mA
I
OL
=24 mA
I
OL
=24 mA
V
IN
=V
CC
or GND
V
OLD
=1.65 V Max
V
OHD
=3.85 V Min
V
IN
=V
CC
or GND
I
IN
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
+Minimum Dynamic
Output Current
+Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
(per Package)
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Note: I
IN
and I
CC
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
CC
3
KK74AC174
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=3.0 ns)
V
CC*
Symbol
Parameter
V
Guaranteed Limits
25
°C
Min
f
max
t
PLH
t
PHL
t
PHL
C
IN
Maximum Clock Frequency (Figure 1)
Propagation Delay, Clock to Q (Figure 1)
Propagation Delay, Clock to Q (Figure 1)
Propagation Delay, Reset to Q (Figure 2)
Maximum Input Capacitance
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
5.0
90
100
2.0
1.5
2.0
1.5
2.5
1.5
4.5
11.5
8.5
11.0
8.0
11.5
9.0
Max
-40°C to
85°C
Min
70
100
1.5
1.0
1.5
1.0
2.0
1.5
4.5
12.5
9.5
12.0
9.0
12.5
10.5
Max
MHz
ns
ns
ns
pF
Unit
Typical @25°C,V
CC
=5.0 V
C
PD
*
Power Dissipation Capacitance
85
pF
Voltage Range 3.3 V is 3.3 V
±0.3
V
Voltage Range 5.0 V is 5.0 V
±0.5
V
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=3.0 ns)
V
CC*
Symbol
t
su
t
h
t
w
t
w
t
rec
*
Guaranteed Limits
25
°C
6.5
5.0
3.0
3.0
5.5
5.0
5.5
5.0
2.5
2.0
-40°C to
85°C
7.0
5.5
3.0
3.0
7.0
5.0
7.0
5.0
2.5
2.0
Unit
ns
ns
ns
ns
ns
Parameter
Minimum Setup Time, Data to Clock
(Figure 3)
Minimum Hold Time, Clock to Data
(Figure 3)
Minimum Pulse Width, Reset (Figure 2)
Minimum Pulse Width, Clock (Figure 1)
Minimum Recovery Time, Reset to Clock
(Figure 2)
V
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Voltage Range 3.3 V is 3.3 V
±0.3
V
Voltage Range 5.0 V is 5.0 V
±0.5
V
4
KK74AC174
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
EXPANDED LOGIC DIAGRAM
5
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