72421L15JG datasheet, PDF - EEWORLD Datasheet

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72421L15JG: DescriptionFIFO, 64X9, 10ns, Synchronous, CMOS, PQCC32, GREEN, PLASTIC, LCC-32; Categorystorage storage; File Size109KB，14 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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72421L15JG Overview

FIFO, 64X9, 10ns, Synchronous, CMOS, PQCC32, GREEN, PLASTIC, LCC-32

72421L15JG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFJ
package instruction	LCC-32
Contacts	32
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	10 ns
period time	15 ns
JESD-30 code	R-PLCC-J32
JESD-609 code	e3
memory density	576 bit
Memory IC Type	OTHER FIFO
memory width	9
Humidity sensitivity level	1
Number of functions	1
Number of terminals	32
word count	64 words
character code	64
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64X9
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
Package shape	RECTANGULAR
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
Maximum standby current	0.005 A
Maximum slew rate	0.035 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	J BEND
Terminal location	QUAD
Maximum time at peak reflow temperature	30
Base Number Matches	1

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LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

CMOS SyncFIFO

™

64 x 9, 256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

4,096 x 9 and 8,192 x 9

IDT72421, IDT72201

IDT72211, IDT72221

IDT72231, IDT72241

IDT72251

FEATURES:

•

64 x 9-bit organization (IDT72421)

256 x 9-bit organization (IDT72201)

512 x 9-bit organization (IDT72211)

1,024 x 9-bit organization (IDT72221)

2,048 x 9-bit organization (IDT72231)

4,096 x 9-bit organization (IDT72241)

8,192 x 9-bit organization (IDT72251)

10 ns read/write cycle time

Read and Write Clocks can be independent

Dual-Ported zero fall-through time architecture

Empty and Full Flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags can be set

to any depth

Programmable Almost-Empty and Almost-Full flags default to

Empty+7, and Full-7, respectively

Output enable puts output data bus in high-impedance state

Advanced submicron CMOS technology

Available in the 32-pin plastic leaded chip carrier (PLCC) and

32-pin Thin Quad Flat Pack (TQFP)

For through-hole product please see the IDT72420/72200/72210/

72220/72230/72240 data sheet

Industrial temperature range (–40°C to +85°C) is available

Green parts available, see ordering information

The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO™

are very high-speed, low-power First-In, First-Out (FIFO) memories with

clocked read and write controls. These devices have a 64, 256, 512, 1,024,

2,048, 4,096, and 8,192 x 9-bit memory array, respectively. These FIFOs are

applicable for a wide variety of data buffering needs such as graphics, local area

networks and interprocessor communication.

These FIFOs have 9-bit input and output ports. The input port is controlled

by a free-running clock (WCLK), and two write enable pins (WEN1, WEN2).

Data is written into the Synchronous FIFO on every rising clock edge when

the write enable pins are asserted. The output port is controlled by another clock

pin (RCLK) and two read enable pins (REN1,

REN2).

The Read Clock can

be tied to the Write Clock for single clock operation or the two clocks can run

asynchronous of one another for dual-clock operation. An output enable pin

(OE) is provided on the read port for three-state control of the output.

The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF).

Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are

provided for improved system control. The programmable flags default to

Empty+7 and Full-7 for

PAE

and

PAF,

respectively. The programmable flag

offset loading is controlled by a simple state machine and is initiated by asserting

the load pin (LD).

These FIFOs are fabricated using high-speed submicron CMOS technology.

DESCRIPTION:

FUNCTIONAL BLOCK DIAGRAM

WCLK

WEN1

WEN2

- D

INPUT REGISTER

OFFSET REGISTER

PAE

PAF

WRITE CONTROL

LOGIC

RAM ARRAY

64 x 9, 256 x 9,

512 x 9, 1,024 x 9,

2,048 x 9, 4,096 x 9,

8,192 x 9

FLAG

LOGIC

WRITE POINTER

READ POINTER

READ CONTROL

LOGIC

OUTPUT REGISTER

RESET LOGIC

RCLK

REN1

REN2

- Q

2655 drw01

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2017

NOVEMBER 2017

DSC-2655/7

72421L15JG Related Products

	72421L15JG	72421L15JGI	72211L15JGI	72201L15JGI	72201L15JG
Description	FIFO, 64X9, 10ns, Synchronous, CMOS, PQCC32, GREEN, PLASTIC, LCC-32	FIFO, 64X9, 10ns, Synchronous, CMOS, PQCC32, GREEN, PLASTIC, LCC-32	FIFO, 512X9, 10ns, Synchronous, CMOS, PQCC32, GREEN, PLASTIC, LCC-32	FIFO, 256X9, 10ns, Synchronous, CMOS, PQCC32, GREEN, PLASTIC, LCC-32	FIFO, 256X9, 10ns, Synchronous, CMOS, PQCC32, GREEN, PLASTIC, LCC-32
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFJ	QFJ	QFJ	QFJ	QFJ
package instruction	LCC-32	,	LCC-32	,	LCC-32
Contacts	32	32	32	32	32
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99
Maximum access time	10 ns	10 ns	10 ns	10 ns	10 ns
period time	15 ns	15 ns	15 ns	15 ns	15 ns
JESD-30 code	R-PLCC-J32	R-PLCC-J32	R-PLCC-J32	R-PLCC-J32	R-PLCC-J32
JESD-609 code	e3	e3	e3	e3	e3
memory density	576 bit	576 bit	4608 bit	2304 bit	2304 bit
Memory IC Type	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO
memory width	9	9	9	9	9
Humidity sensitivity level	1	1	1	1	1
Number of functions	1	1	1	1	1
Number of terminals	32	32	32	32	32
word count	64 words	64 words	512 words	256 words	256 words
character code	64	64	512	256	256
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	85 °C	85 °C	85 °C	70 °C
Minimum operating temperature	-	-40 °C	-40 °C	-40 °C	-
organize	64X9	64X9	512X9	256X9	256X9
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Exportable	YES	YES	YES	YES	YES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	260	260	260
power supply	5 V	5 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum standby current	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A
Maximum slew rate	0.035 mA	0.035 mA	0.035 mA	0.035 mA	0.035 mA
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	J BEND	J BEND	J BEND	J BEND	J BEND
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	30	30	30
Base Number Matches	1	1	1	1	1

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