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www.ti.com
TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q
TPS76728Q, TPS76730Q, TPS76733Q, TPS76750Q, TPS76701Q
FAST TRANSIENT RESPONSE 1 A LOW DROPOUT LINEAR REGULATORS
SLVS208I − MAY 1999 − REVISED JANUARY 2004
D
1 A Low-Dropout Voltage Regulator
D
Available in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V,
D
D
D
D
D
D
D
3.0-V, 3.3-V, 5.0-V Fixed Output and
Adjustable Versions
Dropout Voltage Down to 230 mV at 1 A
(TPS76750)
Ultralow 85
mA
Typical Quiescent Current
Fast Transient Response
2% Tolerance Over Specified Conditions for
Fixed-Output Versions
Open Drain Power-On Reset With 200-ms
Delay (See TPS768xx for PG Option)
8-Pin SOIC and 20-Pin TSSOP PowerPAD
(PWP) Package
Thermal Shutdown Protection
PWP PACKAGE
(TOP VIEW)
GND/HSINK
GND/HSINK
GND
NC
EN
IN
IN
NC
GND/HSINK
GND/HSINK
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND/HSINK
GND/HSINK
NC
NC
RESET
FB/NC
OUT
OUT
GND/HSINK
GND/HSINK
NC − No internal connection
D PACKAGE
(TOP VIEW)
description
This device is designed to have a fast transient
response and be stable with 10
µF
low ESR
capacitors. This combination provides high
performance at a reasonable cost.
TPS76733
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
103
∆
VO − Change in
Output Voltage − mV
IO = 1 A
VDO − Dropout Voltage − mV
102
100
50
0
−50
−100
1
0.5
0
GND
EN
IN
IN
1
2
3
4
8
7
6
5
RESET
FB/NC
OUT
OUT
TPS76733
LOAD TRANSIENT RESPONSE
Co = 10
µF
TA = 25°C
101
100
IO = 10 mA
10−1
Co = 10
µF
−2
10
−60 −40 −20 0
IO = 0
20
40
60
80 100 120 140
I O − Output Current − A
0
TA − Free-Air Temperature −
°C
100 200 300 400 500 600 700 800 900 1000
t − Time −
µs
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright
1999 − 2004, Texas Instruments Incorporated
1
TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q
TPS76728Q, TPS76730Q, TPS76733Q, TPS76750Q, TPS76701Q
FAST TRANSIENT RESPONSE 1 A LOW DROPOUT LINEAR REGULATORS
SLVS208I − MAY 1999 − REVISED JANUARY 2004
www.ti.com
description (continued)
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 230 mV at an output
current of 1 A for the TPS76750) and is directly proportional to the output current. Additionally, since the PMOS pass
element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 85
µA
over
the full range of output current, 0 mA to 1 A). These two key specifications yield a significant improvement in operating life
for battery-powered systems. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts
down the regulator, reducing the quiescent current to 1
µA
at T
J
= 25°C.
The RESET output of the TPS767xx initiates a reset in microcomputer and microprocessor systems in the event of an
undervoltage condition. An internal comparator in the TPS767xx monitors the output voltage of the regulator to detect an
undervoltage condition on the regulated output voltage.
The TPS767xx is offered in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V, and 5.0-V fixed-voltage versions and in an
adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is specified as a maximum
of 2% over line, load, and temperature ranges. The TPS767xx family is available in 8-pin SOIC and 20-pin PWP packages.
AVAILABLE OPTIONS
OUTPUT
VOLTAGE
(V)
TYP
5.0
3.3
3.0
2.8
−40°C to 125°C
2.7
2.5
1.8
1.5
Adjustable
1.5 V to 5.5 V
PACKAGED DEVICES
TSSOP
(PWP)
TPS76750Q
TPS76733Q
TPS76730Q
TPS76728Q
TPS76727Q
TPS76725Q
TPS76718Q
TPS76715Q
TPS76701Q
SOIC
(D)
TPS76750Q
TPS76733Q
TPS76730Q
TPS76728Q
TPS76727Q
TPS76725Q
TPS76718Q
TPS76715Q
TPS76701Q
TJ
The TPS76701 is programmable using an external resistor divider (see application
information). The D and PWP packages are available taped and reeled. Add an R
suffix to the device type (e.g., TPS76701QDR).
TPS767xx
VI
6
7
IN
OUT
0.1
µF
5
EN
GND
3
OUT
14
13
+
Co(1)
10
µF
VO
IN
RESET
16
RESET
(1) See application information section for capacitor selection details.
Figure 1. Typical Application Configuration (For Fixed Output Options)
2
www.ti.com
TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q
TPS76728Q, TPS76730Q, TPS76733Q, TPS76750Q, TPS76701Q
FAST TRANSIENT RESPONSE 1 A LOW DROPOUT LINEAR REGULATORS
SLVS208I − MAY 1999 − REVISED JANUARY 2004
functional block diagram—adjustable version
IN
EN
RESET
_
+
OUT
+
_
Vref = 1.1834 V
200 ms Delay
FB/NC
R1
R2
GND
External to the device
functional block diagram—fixed-voltage version
IN
EN
RESET
_
+
OUT
+
_
Vref = 1.1834 V
200 ms Delay
R1
R2
GND
3
TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q
TPS76728Q, TPS76730Q, TPS76733Q, TPS76750Q, TPS76701Q
FAST TRANSIENT RESPONSE 1 A LOW DROPOUT LINEAR REGULATORS
SLVS208I − MAY 1999 − REVISED JANUARY 2004
www.ti.com
Terminal Functions
SOIC Package
TERMINAL
NAME
EN
FB/NC
GND
IN
OUT
RESET
NO.
2
7
1
3, 4
5, 6
8
I
O
O
I/O
I
I
Enable input
Feedback input voltage for adjustable device (no connect for fixed options)
Regulator ground
Input voltage
Regulated output voltage
RESET output
DESCRIPTION
PWP Package
TERMINAL
NAME
EN
FB/NC
GND
GND/HSINK
IN
NC
OUT
RESET
NO.
5
15
3
1, 2, 9, 10, 11,
12, 19, 20
6, 7
4, 8, 17, 18
13, 14
16
O
O
I
I/O
I
I
Enable input
Feedback input voltage for adjustable device (no connect for fixed options)
Regulator ground
Ground/heatsink
Input voltage
No connect
Regulated output voltage
RESET output
DESCRIPTION
timing diagram
VI
Vres
(1)
t
VO
Threshold
Voltage
VIT−
(2)
Vres
VIT+
(2)
VIT+
(2)
Less than 5% of the
output voltage
VIT−
(2)
t
RESET
Output
200 ms
Delay
200 ms
Delay
Output
Undefined
(1) Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for
semiconductor symbology.
(2) VIT −Trip voltage is typically 5% lower than the output voltage (95%VO) VIT− to VIT+ is the hysteresis voltage.
4
ÎÎ
ÎÎ
ÎÎ
ÎÎ
t
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Output
Undefined
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