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DV74ALS114AN

Description
J-K Flip-Flop, ALS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDIP14, PLASTIC, DIP-14
Categorylogic    logic   
File Size137KB,3 Pages
ManufacturerAVG [AVG Semiconductors(HITEK)]
Download Datasheet Parametric Compare View All

DV74ALS114AN Overview

J-K Flip-Flop, ALS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDIP14, PLASTIC, DIP-14

DV74ALS114AN Parametric

Parameter NameAttribute value
MakerAVG [AVG Semiconductors(HITEK)]
Parts packaging codeDIP
package instructionDIP,
Contacts14
Reach Compliance Codeunknown
Other featuresWITH INDIVIDUAL SET INPUTS
seriesALS
JESD-30 codeR-PDIP-T14
length18.86 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeJ-K FLIP-FLOP
Number of digits2
Number of functions2
Number of terminals14
Maximum operating temperature70 °C
Minimum operating temperature-10 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Maximum supply current (ICC)4.5 mA
propagation delay (tpd)19 ns
Certification statusNot Qualified
Maximum seat height4.69 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Trigger typeNEGATIVE EDGE
width7.62 mm
minfmax30 MHz
Base Number Matches1

DV74ALS114AN Related Products

DV74ALS114AN DV74ALS114AD DV74LS114AN DV74LS114AD
Description J-K Flip-Flop, ALS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDIP14, PLASTIC, DIP-14 J-K Flip-Flop, ALS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO14, PLASTIC, SOP-14 J-K Flip-Flop, LS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDIP14, PLASTIC, DIP-14 J-K Flip-Flop, LS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO14, PLASTIC, SOP-14
Parts packaging code DIP SOIC DIP SOIC
package instruction DIP, SOP, DIP, SOP,
Contacts 14 14 14 14
Reach Compliance Code unknown unknown unknown unknown
Other features WITH INDIVIDUAL SET INPUTS WITH INDIVIDUAL SET INPUTS WITH INDIVIDUAL SET INPUTS WITH INDIVIDUAL SET INPUTS
series ALS ALS LS LS
JESD-30 code R-PDIP-T14 R-PDSO-G14 R-PDIP-T14 R-PDSO-G14
length 18.86 mm 8.65 mm 18.86 mm 8.65 mm
Load capacitance (CL) 50 pF 50 pF 15 pF 15 pF
Logic integrated circuit type J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP
Number of digits 2 2 2 2
Number of functions 2 2 2 2
Number of terminals 14 14 14 14
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C
Minimum operating temperature -10 °C -10 °C -10 °C -10 °C
Output polarity COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP SOP DIP SOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE SMALL OUTLINE IN-LINE SMALL OUTLINE
Maximum supply current (ICC) 4.5 mA 4.5 mA 6 mA 6 mA
propagation delay (tpd) 19 ns 19 ns 20 ns 20 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 4.69 mm 1.75 mm 4.69 mm 1.75 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V
surface mount NO YES NO YES
technology TTL TTL TTL TTL
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form THROUGH-HOLE GULL WING THROUGH-HOLE GULL WING
Terminal pitch 2.54 mm 1.27 mm 2.54 mm 1.27 mm
Terminal location DUAL DUAL DUAL DUAL
Trigger type NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE
width 7.62 mm 3.9 mm 7.62 mm 3.9 mm
minfmax 30 MHz 30 MHz 30 MHz 30 MHz
Maker AVG [AVG Semiconductors(HITEK)] AVG [AVG Semiconductors(HITEK)] - AVG [AVG Semiconductors(HITEK)]
Base Number Matches 1 1 1 -

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