Am75PDL191CHHa/
Am75PDL193CHHa
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
30897
Revision
A
Amendment
+1
Issue Date
January 14, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
ADVANCE INFORMATION
Am75PDL191CHHa/Am75PDL193CHHa
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
with Enhanced Versatile I/O Control and Dual Chip Enable Input plus, for Additional Code
or Data Storage, 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write
Flash Memory and 64 Mbit (4 M x 16-Bit) CMOS Pseudo Static RAM
DISTINCTIVE CHARACTERISTICS
For Code Storage:
Am29PDL127H/Am29PDL129H Features
ARCHITECTURAL ADVANTAGES
■
128 Mbit Page Mode device
— Page size of 8 words: Fast page read access from random
locations within the page
■
Both top and bottom boot blocks in one device
■
Manufactured on 0.13 µm process technology
■
20-year data retention at 125°C
■
Minimum 1 million erase cycle guarantee per sector
PERFORMANCE CHARACTERISTICS
■
High Performance
— Page access times as fast as 30 ns
— Random access times as fast as 70 ns
■
Dual Chip Enable inputs (PDL129 only)
— Two CE inputs control selection of each half of the memory
space
■
Single power supply operation
— Full Voltage range: 2.7 to 3.1 volt read, erase, and program
operations for battery-powered applications
■
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 25 mA program/erase current
— 1 µA typical standby mode current
■
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
SOFTWARE FEATURES
■
Software command-set compatible with JEDEC 42.4
standard
— Backward compatible with Am29F and Am29LV families
■
FlexBank Architecture
— 4 separate banks, with up to two simultaneous operations
per device
■
CFI (Common Flash Interface) complaint
— Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
PDL127:
—
—
—
—
—
—
—
—
Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
Bank B: 48 Mbit (32 Kw x 96)
Bank C: 48 Mbit (32 Kw x 96)
Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
Bank 1A: 48 Mbit (32 Kw x 96)
Bank 1B: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
Bank 2A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
Bank 2B: 48 Mbit (32 Kw x 96)
■
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
operations in other sectors of same bank
PDL129:
■
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
■
SecSi
TM
(Secured Silicon) Sector region
— Up to 128 words accessible through a command sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
30897
Rev:
A
Amendment
+1
Issue Date:
January 14, 2004
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
HARDWARE FEATURES
■
Ready/Busy# pin (RY/BY#)
I N F O R M A T I O N
— Pinout and software compatible with
single-power-supply flash standard
— Provides a hardware method of detecting program or erase
cycle completion
PERFORMANCE CHARACTERISTICS
■
High performance
— Access time as fast as 70 ns
— Program time: 4 µs/word typical utilizing Accelerate
function
■
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■
Minimum 1 million erase cycles guaranteed per
sector
■
20 year data retention at 125°C
— Reliable operation for the life of the system
■
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array data
■
WP#/ACC (Write Protect/Acceleration) input
— At V
IL
, hardware level protection for the first and last two 4K
word sectors.
— At V
IH
, allows removal of sector protection
— At V
HH
, provides accelerated programming in a factory
setting
■
Persistent Sector Protection
— A command sector protection method to lock combinations
of individual sectors and sector groups to prevent program or
erase operations within that sector
— Sectors can be locked and unlocked in-system at V
CC
level
■
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
SOFTWARE FEATURES
■
Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
■
Supports Common Flash Memory Interface (CFI)
■
Erase Suspend/Erase Resume
— Suspends erase operations to allow reading from
other sectors in same bank
■
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
FOR CODE OR DATA STORAGE:
AM29DL640H
■
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
■
Flexible Bank
TM
architecture
— Read may occur in any of the three banks not being
written or erased.
— Four banks may be grouped by customer to achieve
desired bank divisions.
■
Boot Sectors
— Top and bottom boot sectors in the same device
— Any combination of sectors can be erased
■
Manufactured on 0.13 µm process technology
■
SecSi™ (Secured Silicon) Sector: Extra 256 Byte
sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
—
Customer lockable:
One-time programmable only.
Once locked, data cannot be changed
■
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero.
■
Compatible with JEDEC standards
HARDWARE FEATURES
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
■
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
■
WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1,
140, and 141, regardless of sector protect status
— Acceleration (ACC) function accelerates program
timing
■
Sector protection
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
2
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
A D V A N C E
PSRAM FEATURES
■
Organization: 4 M x 16-Bit
■
Power Supply voltage of 2.7 to 3.1 V
■
Three state outputs
■
Compatible with Low Power SRAM
■
Deep Power Down: Memory Cell data hold invalid
I N F O R M A T I O N
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
3
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